-------------------------------------------------------------------------------- Xilinx TRACE, Version C.22 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Design file: multipli.ncd Physical constraint file: multipli.pcf Device,speed: xc4010xl,-3 (C 1.1.2.2 FINAL) Report level: error report -------------------------------------------------------------------------------- WARNING:Timing:181 - No timing constraints found, doing default enumeration. ================================================================================ Timing constraint: Default period analysis 28 items analyzed, 0 timing errors detected. Maximum delay is 25.191ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: Default net enumeration 11 items analyzed, 0 timing errors detected. Maximum net delay is 12.060ns. -------------------------------------------------------------------------------- All constraints were met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Pad to Pad ---------------+---------------+---------+ Source Pad |Destination Pad| Delay | ---------------+---------------+---------+ A<1> |SEGMENTS<0> | 24.013| A<1> |SEGMENTS<1> | 22.897| A<1> |SEGMENTS<2> | 22.231| A<1> |SEGMENTS<3> | 22.159| A<1> |SEGMENTS<4> | 23.409| A<1> |SEGMENTS<5> | 22.394| A<1> |SEGMENTS<6> | 25.191| B<1> |SEGMENTS<0> | 20.866| B<1> |SEGMENTS<1> | 17.660| B<1> |SEGMENTS<2> | 20.142| B<1> |SEGMENTS<3> | 20.453| B<1> |SEGMENTS<4> | 20.763| B<1> |SEGMENTS<5> | 17.157| B<1> |SEGMENTS<6> | 22.044| B<0> |SEGMENTS<0> | 14.802| B<0> |SEGMENTS<1> | 15.578| B<0> |SEGMENTS<2> | 16.067| B<0> |SEGMENTS<3> | 16.626| B<0> |SEGMENTS<4> | 18.356| B<0> |SEGMENTS<5> | 15.075| B<0> |SEGMENTS<6> | 15.980| A<0> |SEGMENTS<0> | 20.321| A<0> |SEGMENTS<1> | 20.869| A<0> |SEGMENTS<2> | 21.856| A<0> |SEGMENTS<3> | 22.806| A<0> |SEGMENTS<4> | 23.638| A<0> |SEGMENTS<5> | 20.366| A<0> |SEGMENTS<6> | 21.499| ---------------+---------------+---------+ Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 28 paths, 11 nets, and 35 connections (100.0% coverage) Design statistics: Maximum combinational path delay: 25.191ns Maximum net delay: 12.060ns Analysis completed Wed Oct 25 18:33:49 2000 --------------------------------------------------------------------------------