PAR: Xilinx Place And Route C.22.
Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.
Wed Oct 25 18:33:41 2000
par -w -ol 2 -d 0 map.ncd multipli.ncd multipli.pcf
Constraints file: multipli.pcf
Loading device database for application par from file "map.ncd".
"multipli" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3
Loading device for application par from file '4010xl.nph' in environment
C:/Fndtn.
Device speed data version: C 1.1.2.2 FINAL.
Resolved that IOB > must be placed at site P7.
Resolved that IOB > must be placed at site P6.
Resolved that IOB > must be placed at site P9.
Resolved that IOB > must be placed at site P8.
Resolved that IOB > must be placed at site P19.
Resolved that IOB > must be placed at site P23.
Resolved that IOB > must be placed at site P26.
Resolved that IOB > must be placed at site P25.
Resolved that IOB > must be placed at site P24.
Resolved that IOB > must be placed at site P18.
Resolved that IOB > must be placed at site P20.
Device utilization summary:
Number of External IOBs 11 out of 61 18%
Flops: 0
Latches: 0
Number of CLBs 4 out of 400 1%
Total Latches: 0 out of 800 0%
Total CLB Flops: 0 out of 800 0%
4 input LUTs: 7 out of 800 1%
3 input LUTs: 0 out of 400 0%
Overall effort level (-ol): 2 (set by user)
Placer effort level (-pl): 2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): 2 (set by user)
Starting initial Placement phase. REAL time: 3 secs
Finished initial Placement phase. REAL time: 4 secs
Starting Constructive Placer. REAL time: 4 secs
Placer score = 7740
Placer score = 3930
Finished Constructive Placer. REAL time: 4 secs
Writing design to file "multipli.ncd".
Starting Optimizing Placer. REAL time: 4 secs
Optimizing
Swapped 26 comps.
Xilinx Placer [1] 2310 REAL time: 4 secs
Finished Optimizing Placer. REAL time: 4 secs
Writing design to file "multipli.ncd".
Total REAL time to Placer completion: 4 secs
Total CPU time to Placer completion: 3 secs
0 connection(s) routed; 35 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 4 secs
Starting iterative routing.
Routing active signals.
End of iteration 1
35 successful; 0 unrouted; (0) REAL time: 4 secs
Constraints are met.
Routing PWR/GND nets.
Power and ground nets completely routed.
Writing design to file "multipli.ncd".
Starting cleanup
Improving routing.
End of cleanup iteration 1
35 successful; 0 unrouted; (0) REAL time: 5 secs
Writing design to file "multipli.ncd".
Total REAL time: 5 secs
Total CPU time: 4 secs
End of route. 35 routed (100.00%); 0 unrouted.
No errors found.
Completely routed.
This design was run without timing constraints. It is likely that much better
circuit performance can be obtained by trying either or both of the following:
- Enabling the Delay Based Cleanup router pass, if not already enabled
- Supplying timing constraints in the input design
Total REAL time to Router completion: 5 secs
Total CPU time to Router completion: 4 secs
Generating PAR statistics.
The Delay Summary Report
The Score for this design is: 766
The Number of signals not completely routed for this design is: 0
The Average Connection Delay for this design is: 6.645 ns
The Maximum Pin Delay is: 12.060 ns
The Average Connection Delay on the 10 Worst Nets is: 5.114 ns
Listing Pin Delays by value: (ns)
d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 13.00 d >= 13.00
--------- --------- --------- --------- --------- ---------
3 8 5 1 18 0
Writing design to file "multipli.ncd".
All signals are completely routed.
Total REAL time to PAR completion: 5 secs
Total CPU time to PAR completion: 4 secs
PAR done.