Xilinx Mapping Report File for Design 'multipli'
Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.

Design Information
------------------
Command Line   : m1map -p xc4010xl-3-pc84 -o map.ncd multipli.ngd multipli.pcf 
Target Device  : x4010xl
Target Package : pc84
Target Speed   : -3
Mapper Version : xc4000xl -- C.22

Design Summary
--------------
   Number of errors:        0
   Number of warnings:      1
   Number of CLBs:              4 out of   400    1%
      CLB Flip Flops:       0
      CLB Latches:          0
      4 input LUTs:         7
      3 input LUTs:         0
   Number of bonded IOBs:      11 out of    65   16%
      IOB Flops:            0
      IOB Latches:          0
Total equivalent gate count for design: 42
Additional JTAG gate count for IOBs:    528

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Design Attributes
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - Added Logic
Section 7 - Expanded Logic
Section 8 - Signal Cross-Reference
Section 9 - Symbol Cross-Reference
Section 10 - IOB Properties
Section 11 - RPMs
Section 12 - Guide Report

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:OldMap:78 - All of the external outputs in this design are using
   slew-rate-limited output drivers.  The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the original
   design.  Please see your vendor interface documentation for specific
   information on how to do this within your design-entry tool.
   Note: You should be careful not to designate too many outputs which switch
   together as fast, because this can cause excessive ground bounce.  For more
   information on this subject, please refer to the IOB switching characteristic
   guidelines for the device you are using in the Programmable Logic Data Book.

Section 3 - Design Attributes
-----------------------------
 Attribute LOC
   "P6" on symbol "A<1>.PAD"
   "P7" on symbol "A<0>.PAD"
   "P8" on symbol "B<1>.PAD"
   "P9" on symbol "B<0>.PAD"
   "P20" for signal(s) SEGMENTS<6> on symbol "SEGMENTS<6>.PAD"
   "P18" for signal(s) SEGMENTS<5> on symbol "SEGMENTS<5>.PAD"
   "P24" for signal(s) SEGMENTS<4> on symbol "SEGMENTS<4>.PAD"
   "P25" for signal(s) SEGMENTS<3> on symbol "SEGMENTS<3>.PAD"
   "P26" for signal(s) SEGMENTS<2> on symbol "SEGMENTS<2>.PAD"
   "P23" for signal(s) SEGMENTS<1> on symbol "SEGMENTS<1>.PAD"
   "P19" for signal(s) SEGMENTS<0> on symbol "SEGMENTS<0>.PAD"

Section 4 - Removed Logic Summary
---------------------------------

Section 5 - Removed Logic
-------------------------

Section 6 - Added Logic
-----------------------

Section 7 - Expanded Logic
--------------------------
To enable this section, set the detailed map report option and rerun map.

Section 8 - Signal Cross-Reference
----------------------------------
To enable this section, set the detailed map report option and rerun map.

Section 9 - Symbol Cross-Reference
----------------------------------
To enable this section, set the detailed map report option and rerun map.

Section 10 - IOB Properties
---------------------------
"SEGMENTS<0>" (IOB) : SLEW=SLOW
"SEGMENTS<1>" (IOB) : SLEW=SLOW
"SEGMENTS<2>" (IOB) : SLEW=SLOW
"SEGMENTS<3>" (IOB) : SLEW=SLOW
"SEGMENTS<4>" (IOB) : SLEW=SLOW
"SEGMENTS<5>" (IOB) : SLEW=SLOW
"SEGMENTS<6>" (IOB) : SLEW=SLOW

Section 11 - RPMs
-----------------

Section 12 - Guide Report
-------------------------
Guide not run on this design.