ngdbuild -p xc4010xl-3-pc84 -uc multipli.ucf -dd .. c:\ec333_~2\labs\lab7xi~1\multipli\multipli.xnf multipli.ngd
ngdbuild: version C.22
Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -p xc4010xl-3-pc84 -uc multipli.ucf -dd ..
c:\ec333_~2\labs\lab7xi~1\multipli\multipli.xnf multipli.ngd
Launcher: Executing xnf2ngd -p xc4000xl -u
"c:\ec333_~2\labs\lab7xi~1\multipli\multipli.xnf" "C:\EC333_Fall2000 digital
systems\labs\lab 7 xilinx\multipli\xproj\ver1\multipli.ngo"
xnf2ngd: version C.22
Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.
using XNF gate model
reading XNF file "c:/ec333_~2/labs/lab7xi~1/multipli/multipli.xnf" ...
Writing NGO file "C:/EC333_Fall2000 digital systems/labs/lab 7
xilinx/multipli/xproj/ver1/multipli.ngo" ...
Reading NGO file "C:/EC333_Fall2000 digital systems/labs/lab 7
xilinx/multipli/xproj/ver1/multipli.ngo" ...
Reading component libraries for design expansion...
Annotating constraints to design from file "multipli.ucf" ...
Checking timing specifications ...
Checking expanded design ...
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGD file "multipli.ngd" ...
Writing NGDBUILD log file "multipli.bld"...
NGDBUILD done.
==================================================
map -p xc4010xl-3-pc84 -o map.ncd multipli.ngd multipli.pcf
map: version C.22
Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.
Reading NGD file "multipli.ngd"...
Using target part "4010xlpc84-3".
MAP xc4000xl directives:
Partname = "xc4010xl-3-pc84".
Covermode = "area".
Pack Unrelated Logic into CLBs targeting 100% of CLB resources.
Processing logical timing constraints...
Verifying F/HMAP validity based on pre-trimmed logic...
Removing unused logic...
Packing logic in CLBs...
Running cover...
Undirected packing...
Running physical design DRC...
Design Summary:
Number of errors: 0
Number of warnings: 1
Number of CLBs: 4 out of 400 1%
CLB Flip Flops: 0
CLB Latches: 0
4 input LUTs: 7
3 input LUTs: 0
Number of bonded IOBs: 11 out of 65 16%
IOB Flops: 0
IOB Latches: 0
Total equivalent gate count for design: 42
Additional JTAG gate count for IOBs: 528
Writing design file "map.ncd"...
Mapping completed.
See MAP report file "map.mrp" for details.
==================================================
par -w -ol 2 -d 0 map.ncd multipli.ncd multipli.pcf
PAR: Xilinx Place And Route C.22.
Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.
Constraints file: multipli.pcf
Loading device database for application par from file "map.ncd".
"multipli" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3
Loading device for application par from file '4010xl.nph' in environment
C:/Fndtn.
Device speed data version: C 1.1.2.2 FINAL.
Resolving physical constraints.
Finished resolving physical constraints.
Device utilization summary:
Number of External IOBs 11 out of 61 18%
Flops: 0
Latches: 0
Number of CLBs 4 out of 400 1%
Total Latches: 0 out of 800 0%
Total CLB Flops: 0 out of 800 0%
4 input LUTs: 7 out of 800 1%
3 input LUTs: 0 out of 400 0%
Overall effort level (-ol): 2 (set by user)
Placer effort level (-pl): 2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): 2 (set by user)
Starting initial Placement phase. REAL time: 3 secs
Finished initial Placement phase. REAL time: 4 secs
Starting Constructive Placer. REAL time: 4 secs
Placer score = 7740
Placer score = 3930
Finished Constructive Placer. REAL time: 4 secs
Writing design to file "multipli.ncd".
Starting Optimizing Placer. REAL time: 4 secs
Optimizing
Swapped 26 comps.
Xilinx Placer [1] 2310 REAL time: 4 secs
Finished Optimizing Placer. REAL time: 4 secs
Writing design to file "multipli.ncd".
Total REAL time to Placer completion: 4 secs
Total CPU time to Placer completion: 3 secs
0 connection(s) routed; 35 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 4 secs
Starting iterative routing.
Routing active signals.
End of iteration 1
35 successful; 0 unrouted; (0) REAL time: 4 secs
Constraints are met.
Routing PWR/GND nets.
Power and ground nets completely routed.
Writing design to file "multipli.ncd".
Starting cleanup
Improving routing.
End of cleanup iteration 1
35 successful; 0 unrouted; (0) REAL time: 5 secs
Writing design to file "multipli.ncd".
Total REAL time: 5 secs
Total CPU time: 4 secs
End of route. 35 routed (100.00%); 0 unrouted.
No errors found.
Completely routed.
This design was run without timing constraints. It is likely that much better
circuit performance can be obtained by trying either or both of the following:
- Enabling the Delay Based Cleanup router pass, if not already enabled
- Supplying timing constraints in the input design
Total REAL time to Router completion: 5 secs
Total CPU time to Router completion: 4 secs
Generating PAR statistics.
Writing design to file "multipli.ncd".
All signals are completely routed.
Total REAL time to PAR completion: 5 secs
Total CPU time to PAR completion: 4 secs
PAR done.
==================================================
trce multipli.ncd multipli.pcf -e 3 -o multipli.twr
Xilinx TRACE, Version C.22
Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.
Loading device database for application trce from file "multipli.ncd".
"multipli" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3
Loading device for application trce from file '4010xl.nph' in environment
C:/Fndtn.
--------------------------------------------------------------------------------
Xilinx TRACE, Version C.22
Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.
Design file: multipli.ncd
Physical constraint file: multipli.pcf
Device,speed: xc4010xl,-3 (C 1.1.2.2 FINAL)
Report level: error report
--------------------------------------------------------------------------------
WARNING:Timing:181 - No timing constraints found, doing default enumeration.
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 28 paths, 11 nets, and 35 connections (100.0% coverage)
Design statistics:
Maximum combinational path delay: 25.191ns
Maximum net delay: 12.060ns
Analysis completed Wed Oct 25 18:33:49 2000
--------------------------------------------------------------------------------
Total time: 3 secs
==================================================
ngdanno multipli.ncd map.ngm
ngdanno: version C.22
Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.
Loading device database for application ngdanno from file "multipli.ncd".
"multipli" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3
Loading device for application ngdanno from file '4010xl.nph' in environment
C:/Fndtn.
Reading .ngm file "map.ngm"...
Building NGA image...
Annotating NGA image...
Distributing delays...
Writing .nga file "multipli.nga"...
15 logical models annotated
==================================================
ngd2edif -w -v fndtn multipli.nga time_sim.edn
ngd2edif: version C.22
Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.
writing only delay properties to EDIF file
dedicated signals will be given global scope
running NGD DRC ...
writing EDIF file to 'time_sim.edn' ...
==================================================
xcpy time_sim.edn c:\ec333_~2\labs\lab7xi~1\multipli\time_sim.edn
==================================================
bitgen multipli.ncd -l -w -f bitgen.ut
BITGEN: Xilinx Bitstream Generator C.22
Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.
Loading device database for application Bitgen from file "multipli.ncd".
"multipli" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3
Loading device for application Bitgen from file '4010xl.nph' in environment
C:/Fndtn.
Opened constraints file multipli.pcf.
Wed Oct 25 18:34:02 2000
Running DRC.
DRC detected 0 errors and 0 warnings.
Saving ll file in "multipli.ll".
Creating bit map...
Saving bit stream in "multipli.bit".
==================================================
xcpy multipli.bit c:\ec333_~2\labs\lab7xi~1\multipli\multipli.bit
==================================================
xcpy multipli.ll c:\ec333_~2\labs\lab7xi~1\multipli\multipli.ll