| Name: multiplier.cmd
|Test script for Verilog 2-bit multiplier
| Written by: Jianjian Song, October 2000 
delete_signals
clpr sim_out.out
restart
| set up input vector, which will be displayed automatically
| display these signals in waveform window
watch FIRST[6:0]
watch SECOND[6:0]
watch THIRD[6:0]
watch FOURTH[6:0]
|--------------------------
| set the clock step size
stepsize 50.0ns
cycle
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