Reading in the Synopsys verilog primitives.

Statistics for case statements in always block at line 9 in file
        'C:/ec333_~2/labs/lab7xi~1/multipli/multiplier.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            11            |    auto/auto     |
===============================================
Writing to hnl file 'c:\EC333_Fall2000 digital systems\labs\lab 7 xilinx\multipli\multipli/workdirs/WORK/multiplier.hnl'
Warning: Variable 'product' is being read 
	in routine multiplier line 9 in file 'C:/ec333_~2/labs/lab7xi~1/multipli/multiplier.v',
	but does not occur in the timing control of the block which begins
	there.   (HDL-180)