| Name: adder.cmd
|Test script for Verilog SN74LS83 4-Bit Adder
| Written by: Jianjian Song, October 2000 
|========================SETUP the Stimulus environment==============
|delete any existing waveforms in the window
|
delete_signals
|--------------------------
| Clear the the file sim_out.out for capturing output directed
| to this file later. This file can be used by Multiple commands
| like BREAK and PRINT to output simulation information.
|
clpr sim_out.out
|--------------------------
| Restart to time zero
|
restart
| set up input vector, which will be displayed automatically
vector INPUT_VEC C0 A[4:1] B[4:1]
vector	SUM	SUM[4:1]
| display these signals in waveform window
watch SUM
watch C4
|--------------------------
| set the clock step size
stepsize 50.0ns
| Assign a value to input vector and clock once with cycle
assign INPUT_VEC 0
cycle
assign INPUT_VEC 085\H
cycle
assign INPUT_VEC 099\H
cycle
assign INPUT_VEC 185\H
cycle
assign INPUT_VEC 1FF\H
cycle
assign INPUT_VEC 176\H
cycle
assign INPUT_VEC 0AB\H
cycle
assign INPUT_VEC 1CD\H
cycle
assign INPUT_VEC 01F\H
cycle
assign INPUT_VEC 177\H
cycle
assign INPUT_VEC 0F7\H
cycle
assign INPUT_VEC 111\H
cycle
| save results in a file
print sim_out.out