module dm7442a (A, B, C, D, OUTPUT) ;
// Written by: Anna Yokel
input A ;
input B ;
input C ;
input D ;
output [9:0] OUTPUT ;

//declarations:
reg A;
reg B;
reg C;
reg D;
reg [9:0] OUTPUT;
reg [4:1] temp;

//code:
always @ (A or B or C or D)
begin
temp[1] <= A;
temp[2] <= B;
temp[3] <= C;
temp[4] <= D;
case (temp)
0: OUTPUT <= 10'b0111111111;
1: OUTPUT <= 10'b1011111111;
2: OUTPUT <= 10'b1101111111;
3: OUTPUT <= 10'b1110111111;
4: OUTPUT <= 10'b1111011111;
5: OUTPUT <= 10'b1111101111;
6: OUTPUT <= 10'b1111110111;
7: OUTPUT <= 10'b1111111011;
8: OUTPUT <= 10'b1111111101;
9: OUTPUT <= 10'b1111111110;
default: OUTPUT <= 10'b1111111111;
endcase
end
endmodule