ngdbuild -p xc4010xl-3-pc84 -uc counter.ucf -dd .. c:\ec333_~2\labs\project\counter\counter.xnf counter.ngd ngdbuild: version C.22 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc4010xl-3-pc84 -uc counter.ucf -dd .. c:\ec333_~2\labs\project\counter\counter.xnf counter.ngd Launcher: Executing xnf2ngd -p xc4000xl -u "c:\ec333_~2\labs\project\counter\counter.xnf" "C:\EC333_Fall2000 digital systems\labs\project\counter\xproj\ver1\counter.ngo" xnf2ngd: version C.22 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. using XNF gate model reading XNF file "c:/ec333_~2/labs/project/counter/counter.xnf" ... Writing NGO file "C:/EC333_Fall2000 digital systems/labs/project/counter/xproj/ver1/counter.ngo" ... Reading NGO file "C:/EC333_Fall2000 digital systems/labs/project/counter/xproj/ver1/counter.ngo" ... Reading component libraries for design expansion... Annotating constraints to design from file "counter.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "counter.ngd" ... Writing NGDBUILD log file "counter.bld"... NGDBUILD done. ================================================== map -p xc4010xl-3-pc84 -o map.ncd counter.ngd counter.pcf map: version C.22 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Reading NGD file "counter.ngd"... Using target part "4010xlpc84-3". MAP xc4000xl directives: Partname = "xc4010xl-3-pc84". Covermode = "area". Pack Unrelated Logic into CLBs targeting 100% of CLB resources. Processing logical timing constraints... Verifying F/HMAP validity based on pre-trimmed logic... Removing unused logic... Packing logic in CLBs... Running cover... Undirected packing... Running physical design DRC... Design Summary: Number of errors: 0 Number of warnings: 1 Number of CLBs: 33 out of 400 8% CLB Flip Flops: 24 CLB Latches: 0 4 input LUTs: 62 3 input LUTs: 4 (1 used as route-throughs) Number of bonded IOBs: 30 out of 65 46% IOB Flops: 0 IOB Latches: 0 Number of clock IOB pads: 1 out of 12 8% Number of BUFGLSs: 1 out of 8 12% Total equivalent gate count for design: 529 Additional JTAG gate count for IOBs: 1440 Writing design file "map.ncd"... Removed Logic Summary: Mapping completed. See MAP report file "map.mrp" for details. ================================================== par -w -ol 2 -d 0 map.ncd counter.ncd counter.pcf PAR: Xilinx Place And Route C.22. Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Constraints file: counter.pcf Loading device database for application par from file "map.ncd". "counter" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3 Loading device for application par from file '4010xl.nph' in environment C:/Fndtn. Device speed data version: C 1.1.2.2 FINAL. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 29 out of 61 47% Flops: 0 Latches: 0 Number of Global Buffer IOBs 1 out of 8 12% Flops: 0 Latches: 0 Number of CLBs 33 out of 400 8% Total Latches: 0 out of 800 0% Total CLB Flops: 24 out of 800 3% 4 input LUTs: 62 out of 800 7% 3 input LUTs: 4 out of 400 1% Number of BUFGLSs 1 out of 8 12% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (set by user) Starting initial Placement phase. REAL time: 4 secs Finished initial Placement phase. REAL time: 4 secs Starting Constructive Placer. REAL time: 4 secs Placer score = 26070 Placer score = 18660 Placer score = 14730 Placer score = 14370 Placer score = 13770 Placer score = 13740 Placer score = 13290 Placer score = 11610 Placer score = 11310 Placer score = 10980 Placer score = 10320 Placer score = 10200 Placer score = 9930 Finished Constructive Placer. REAL time: 5 secs Writing design to file "counter.ncd". Starting Optimizing Placer. REAL time: 5 secs Optimizing Swapped 18 comps. Xilinx Placer [1] 9540 REAL time: 6 secs Finished Optimizing Placer. REAL time: 6 secs Writing design to file "counter.ncd". Total REAL time to Placer completion: 6 secs Total CPU time to Placer completion: 5 secs 0 connection(s) routed; 276 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 6 secs Starting iterative routing. Routing active signals. End of iteration 1 276 successful; 0 unrouted; (0) REAL time: 7 secs Constraints are met. Routing PWR/GND nets. Power and ground nets completely routed. Writing design to file "counter.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 276 successful; 0 unrouted; (0) REAL time: 8 secs Writing design to file "counter.ncd". Total REAL time: 8 secs Total CPU time: 7 secs End of route. 276 routed (100.00%); 0 unrouted. No errors found. Completely routed. This design was run without timing constraints. It is likely that much better circuit performance can be obtained by trying either or both of the following: - Enabling the Delay Based Cleanup router pass, if not already enabled - Supplying timing constraints in the input design Total REAL time to Router completion: 8 secs Total CPU time to Router completion: 7 secs Generating PAR statistics. Writing design to file "counter.ncd". All signals are completely routed. Total REAL time to PAR completion: 8 secs Total CPU time to PAR completion: 8 secs PAR done. ================================================== trce counter.ncd counter.pcf -e 3 -o counter.twr Xilinx TRACE, Version C.22 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Loading device database for application trce from file "counter.ncd". "counter" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3 Loading device for application trce from file '4010xl.nph' in environment C:/Fndtn. -------------------------------------------------------------------------------- Xilinx TRACE, Version C.22 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Design file: counter.ncd Physical constraint file: counter.pcf Device,speed: xc4010xl,-3 (C 1.1.2.2 FINAL) Report level: error report -------------------------------------------------------------------------------- WARNING:Timing:181 - No timing constraints found, doing default enumeration. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 382 paths, 66 nets, and 276 connections (100.0% coverage) Design statistics: Minimum period: 21.311ns (Maximum frequency: 46.924MHz) Maximum combinational path delay: 23.106ns Maximum net delay: 7.125ns Analysis completed Thu Nov 02 06:22:08 2000 -------------------------------------------------------------------------------- Total time: 4 secs ================================================== ngdanno counter.ncd map.ngm ngdanno: version C.22 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Loading device database for application ngdanno from file "counter.ncd". "counter" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3 Loading device for application ngdanno from file '4010xl.nph' in environment C:/Fndtn. Reading .ngm file "map.ngm"... Building NGA image... Annotating NGA image... Distributing delays... Writing .nga file "counter.nga"... 64 logical models annotated ================================================== ngd2edif -w -v fndtn counter.nga time_sim.edn ngd2edif: version C.22 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. writing only delay properties to EDIF file dedicated signals will be given global scope running NGD DRC ... writing EDIF file to 'time_sim.edn' ... ================================================== xcpy time_sim.edn c:\ec333_~2\labs\project\counter\time_sim.edn ================================================== bitgen counter.ncd -l -w -f bitgen.ut BITGEN: Xilinx Bitstream Generator C.22 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Loading device database for application Bitgen from file "counter.ncd". "counter" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3 Loading device for application Bitgen from file '4010xl.nph' in environment C:/Fndtn. Opened constraints file counter.pcf. Thu Nov 02 06:22:24 2000 Running DRC. DRC detected 0 errors and 0 warnings. Saving ll file in "counter.ll". Creating bit map... Saving bit stream in "counter.bit". ================================================== xcpy counter.bit c:\ec333_~2\labs\project\counter\counter.bit ================================================== xcpy counter.ll c:\ec333_~2\labs\project\counter\counter.ll