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Xilinx TRACE, Version C.22
Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.

Design file:              counter.ncd
Physical constraint file: counter.pcf
Device,speed:             xc4010xl,-3 (C 1.1.2.2 FINAL)
Report level:             error report
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WARNING:Timing:181 - No timing constraints found, doing default enumeration.

================================================================================
Timing constraint: Default period analysis
 382 items analyzed, 0 timing errors detected.
 Minimum period is  21.311ns.
 Maximum delay is  23.106ns.
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================================================================================
Timing constraint: Default net enumeration
 66 items analyzed, 0 timing errors detected.
 Maximum net delay is   7.125ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLK
---------------+------------+------------+
               |  Setup to  |  Hold to   |
Source Pad     | clk (edge) | clk (edge) |
---------------+------------+------------+
_STOP          |    7.175(R)|    0.000(R)|
---------------+------------+------------+

Clock CLK to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
FIRST<0>       |   20.064(R)|
FIRST<1>       |   19.593(R)|
FIRST<2>       |   20.143(R)|
FIRST<3>       |   20.963(R)|
FIRST<4>       |   21.273(R)|
FIRST<5>       |   21.275(R)|
FIRST<6>       |   22.227(R)|
FOURTH<0>      |   19.054(R)|
FOURTH<1>      |   19.423(R)|
FOURTH<2>      |   19.623(R)|
FOURTH<3>      |   19.356(R)|
FOURTH<4>      |   18.226(R)|
FOURTH<5>      |   18.046(R)|
FOURTH<6>      |   20.581(R)|
SECOND<0>      |   23.461(R)|
SECOND<1>      |   23.920(R)|
SECOND<2>      |   22.458(R)|
SECOND<3>      |   22.360(R)|
SECOND<4>      |   22.667(R)|
SECOND<5>      |   23.650(R)|
SECOND<6>      |   25.847(R)|
THIRD<0>       |   19.522(R)|
THIRD<1>       |   21.882(R)|
THIRD<2>       |   19.967(R)|
THIRD<3>       |   18.275(R)|
THIRD<4>       |   17.757(R)|
THIRD<5>       |   19.368(R)|
THIRD<6>       |   19.119(R)|
---------------+------------+

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|
Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|
---------------+---------+---------+---------+---------+
CLK            |   21.255|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 382 paths, 66 nets, and 276 connections (100.0% coverage)

Design statistics:
   Minimum period:  21.311ns (Maximum frequency:  46.924MHz)
   Maximum combinational path delay:  23.106ns
   Maximum net delay:   7.125ns


Analysis completed Thu Nov 02 06:22:08 2000
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