PAR: Xilinx Place And Route C.22.
Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.

Thu Nov 02 06:21:54 2000

par -w -ol 2 -d 0 map.ncd counter.ncd counter.pcf


Constraints file: counter.pcf

Loading device database for application par from file "map.ncd".
   "counter" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3
Loading device for application par from file '4010xl.nph' in environment
C:/Fndtn.
Device speed data version:  C 1.1.2.2 FINAL.


Resolved that CLKIOB <CLK> must be placed at site P35.
Resolved that IOB <FIRST<0>> must be placed at site P19.
Resolved that IOB <FIRST<1>> must be placed at site P23.
Resolved that IOB <FIRST<2>> must be placed at site P26.
Resolved that IOB <FIRST<3>> must be placed at site P25.
Resolved that IOB <FIRST<4>> must be placed at site P24.
Resolved that IOB <FIRST<5>> must be placed at site P18.
Resolved that IOB <FIRST<6>> must be placed at site P20.
Resolved that IOB <FOURTH<0>> must be placed at site P50.
Resolved that IOB <FOURTH<1>> must be placed at site P51.
Resolved that IOB <FOURTH<2>> must be placed at site P57.
Resolved that IOB <FOURTH<3>> must be placed at site P58.
Resolved that IOB <FOURTH<4>> must be placed at site P59.
Resolved that IOB <FOURTH<5>> must be placed at site P60.
Resolved that IOB <FOURTH<6>> must be placed at site P68.
Resolved that IOB <SECOND<0>> must be placed at site P3.
Resolved that IOB <SECOND<1>> must be placed at site P4.
Resolved that IOB <SECOND<2>> must be placed at site P5.
Resolved that IOB <SECOND<3>> must be placed at site P6.
Resolved that IOB <SECOND<4>> must be placed at site P7.
Resolved that IOB <SECOND<5>> must be placed at site P8.
Resolved that IOB <SECOND<6>> must be placed at site P9.
Resolved that IOB <THIRD<0>> must be placed at site P29.
Resolved that IOB <THIRD<1>> must be placed at site P36.
Resolved that IOB <THIRD<2>> must be placed at site P37.
Resolved that IOB <THIRD<3>> must be placed at site P38.
Resolved that IOB <THIRD<4>> must be placed at site P39.
Resolved that IOB <THIRD<5>> must be placed at site P40.
Resolved that IOB <THIRD<6>> must be placed at site P41.
Resolved that IOB <_STOP> must be placed at site P80.


Device utilization summary:

   Number of External IOBs            29 out of 61     47%
      Flops:                           0
      Latches:                         0
   Number of Global Buffer IOBs        1 out of 8      12%
      Flops:                           0
      Latches:                         0

   Number of CLBs                     33 out of 400     8%
      Total Latches:                   0 out of 800     0%
      Total CLB Flops:                24 out of 800     3%
      4 input LUTs:                   62 out of 800     7%
      3 input LUTs:                    4 out of 400     1%

   Number of BUFGLSs                   1 out of 8      12%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)

Starting initial Placement phase.  REAL time: 4 secs 
Finished initial Placement phase.  REAL time: 4 secs 

Starting Constructive Placer.  REAL time: 4 secs 
Placer score = 26070
Placer score = 18660
Placer score = 14730
Placer score = 14370
Placer score = 13770
Placer score = 13740
Placer score = 13290
Placer score = 11610
Placer score = 11310
Placer score = 10980
Placer score = 10320
Placer score = 10200
Placer score = 9930
Finished Constructive Placer.  REAL time: 5 secs 

Writing design to file "counter.ncd".

Starting Optimizing Placer.  REAL time: 5 secs 
Optimizing  
Swapped 18 comps.
Xilinx Placer [1]   9540   REAL time: 6 secs 

Finished Optimizing Placer.  REAL time: 6 secs 

Writing design to file "counter.ncd".

Total REAL time to Placer completion: 6 secs 
Total CPU time to Placer completion: 5 secs 

0 connection(s) routed; 276 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 6 secs 
Starting iterative routing. 
Routing active signals.
End of iteration 1 
276 successful; 0 unrouted; (0) REAL time: 7 secs 
Constraints are met. 
Routing PWR/GND nets.
Power and ground nets completely routed. 
Writing design to file "counter.ncd".
Starting cleanup 
Improving routing.
End of cleanup iteration 1 
276 successful; 0 unrouted; (0) REAL time: 8 secs 
Writing design to file "counter.ncd".
Total REAL time: 8 secs 
Total CPU  time: 7 secs 
End of route.  276 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 8 secs 
Total CPU time to Router completion: 7 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 412


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        2.954 ns
   The Maximum Pin Delay is:                               7.125 ns
   The Average Connection Delay on the 10 Worst Nets is:   5.860 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 8.00  d >= 8.00
   ---------   ---------   ---------   ---------   ---------   ---------
          29          42          87          59          59           0

Writing design to file "counter.ncd".


All signals are completely routed.

Total REAL time to PAR completion: 8 secs 
Total CPU time to PAR completion: 8 secs 

PAR done.