| Name: topcounter.cmd
|Test script for Verilog decimal counter with 7-segment display
| Written by: Jianjian Song, October 2000 
delete_signals
clpr sim_out.out
restart
vector Digit1 FIRST[6:0]
vector Digit2 SECOND[6:0]
vector Digit3 THIRD[6:0]
vector Digit4 FOURTH[6:0]
| set up input vector, which will be displayed automatically
| display these signals in waveform window
|--------------------------
| set the clock step size
stepsize 50.0ns
clock CLK 0 1	|| clock period is 100 ns
assign _STOP 1\B
cycle
assign _STOP 0\B
sim 100ns
assign _STOP 1\B
| execute the following to see Digit1
 sim 1400ns
| execute the following to see Digit2
| sim 5us	
| execute the following to see Digit3
| sim 50us	
| execute the following to see Digit4
| sim 500us