===================
Chip ver1-Optimized
===================

Summary Information:
--------------------
Type: Optimized implementation
Source: ver1, up to date
Status: 0 errors, 5 warnings, 0 messages
Export: exported after last optimization

Target Information:
-------------------
Vendor: Xilinx
Family: XC4000XL
Device: 4010XLPC84
Speed: xl-3

Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: Low
Frequency: 50 MHz
Is module: No
Keep io pads: No
Number of flip-flops: 0
Number of latches: 0

Chip Design Hierarchy:
----------------------
bcd_counter: defined in c:\ec333_~2\labs\lab8\counter\counter.v

Primitive reference count:
--------------------------
FMAP         28
IBUF          1
OBUF         28

Clocks:
-------
                           Required  Estimated                       
Period   Rise     Fall     Freq      Freq       Signal               
(ns)     (ns)     (ns)     (MHz)     (MHz)                           
...............................................................
 20        0       10       50.00     -1.00     default              

Timing Groups:
--------------
                                                              
                                                              
Name                 Description                              
............................................................
(I)                  Input ports                              
(O)                  Output ports                             

Timing Path Groups:
-------------------
                                          Required   Estimated  
                                          Delay      Delay      
From                 To                   (ns)       (ns)       
............................................................
(I)                  (O)                     n/a        n/a     

Input Port Timing:
------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       To-Group             
............................................................
CLOCK                   n/a        n/a     (O)                  

Output Port Timing:
-------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       From-Group           
............................................................
FIRST<6>                n/a        n/a     (I)                  
FIRST<5>                n/a        n/a     (I)                  
FIRST<4>                n/a        n/a     (I)                  
FIRST<3>                n/a        n/a     (I)                  
FIRST<2>                n/a        n/a     (I)                  
FIRST<1>                n/a        n/a     (I)                  
FIRST<0>                n/a        n/a     (I)                  
SECOND<6>               n/a        n/a     (I)                  
SECOND<5>               n/a        n/a     (I)                  
SECOND<4>               n/a        n/a     (I)                  
SECOND<3>               n/a        n/a     (I)                  
SECOND<2>               n/a        n/a     (I)                  
SECOND<1>               n/a        n/a     (I)                  
SECOND<0>               n/a        n/a     (I)                  
THIRD<6>                n/a        n/a     (I)                  
THIRD<5>                n/a        n/a     (I)                  
THIRD<4>                n/a        n/a     (I)                  
THIRD<3>                n/a        n/a     (I)                  
THIRD<2>                n/a        n/a     (I)                  
THIRD<1>                n/a        n/a     (I)                  
THIRD<0>                n/a        n/a     (I)                  
FOURTH<6>               n/a        n/a     (I)                  
FOURTH<5>               n/a        n/a     (I)                  
FOURTH<4>               n/a        n/a     (I)                  
FOURTH<3>               n/a        n/a     (I)                  
FOURTH<2>               n/a        n/a     (I)                  
FOURTH<1>               n/a        n/a     (I)                  
FOURTH<0>               n/a        n/a     (I)                  

Critical Path Timing:
---------------------
           Arrival    Required                                
Cell       Time       Time       Fanout                       
Type       (ns)       (ns)       Count   Pin-Name             
.........................................................