--
-- Written by Synplicity
-- Tue Oct 31 12:53:02 2000
--

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity DFF_FD1E is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CP :  in std_logic;
  EN :  in std_logic;
  R :  in std_logic);
end DFF_FD1E;

architecture beh of DFF_FD1E is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal Q_4 : std_logic ;
  signal Q_INTERNAL : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  Q_4 <= Q_INTERNAL after 100 ps when EN = '0' else D after 100 ps;
  II_Q: prim_dff port map (Q_INTERNAL, Q_4, CP, R, '0');
  Q <= Q_INTERNAL;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity XINPUT is
port(
  Z0 :  out std_logic;
  XI0 :  in std_logic);
end XINPUT;

architecture beh of XINPUT is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  Z0 <= XI0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity XOUTPUT is
port(
  XO0 :  out std_logic;
  A0 :  in std_logic);
end XOUTPUT;

architecture beh of XOUTPUT is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  XO0 <= A0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity DFF_FD is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CP :  in std_logic;
  R :  in std_logic);
end DFF_FD;

architecture beh of DFF_FD is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  II_Q: prim_dff port map (Q, D, CP, R, '0');
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity OR2 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic);
end OR2;

architecture beh of OR2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  Z0 <= A0 or A1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity AND2 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic);
end AND2;

architecture beh of AND2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  Z0 <= A0 and A1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity INV is
port(
  ZN0 :  out std_logic;
  A0 :  in std_logic);
end INV;

architecture beh of INV is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  ZN0 <= not A0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity FD11E is
port(
  Q0 :  out std_logic;
  D0 :  in std_logic;
  CLK :  in std_logic;
  EN :  in std_logic);
end FD11E;

architecture beh of FD11E is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component DFF_FD1E
    port(Q :  out std_logic;
    D :  in std_logic;
    CP :  in std_logic;
    EN :  in std_logic;
    R :  in std_logic  );
  end component;
begin
  II_BLK2: DFF_FD1E port map (
    Q => Q0,
    D => D0,
    CP => CLK,
    EN => EN,
    R => NN_1);
  NN_2 <= '1';
  NN_1 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity IB11 is
port(
  Z0 :  out std_logic;
  XI0 :  in std_logic);
end IB11;

architecture beh of IB11 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component XINPUT
    port(Z0 :  out std_logic;
    XI0 :  in std_logic  );
  end component;
begin
  \II_$1I45\: XINPUT port map (
    Z0 => Z0,
    XI0 => XI0);
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity MUX2 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic;
  S0 :  in std_logic);
end MUX2;

architecture beh of MUX2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal \$1N8\ : std_logic ;
  signal \$1N22\ : std_logic ;
  signal \$1N6\ : std_logic ;
  component AND2
    port(Z0 :  out std_logic;
    A0 :  in std_logic;
    A1 :  in std_logic  );
  end component;
  component OR2
    port(Z0 :  out std_logic;
    A0 :  in std_logic;
    A1 :  in std_logic  );
  end component;
  component INV
    port(ZN0 :  out std_logic;
    A0 :  in std_logic  );
  end component;
begin
  \II_$1I25\: AND2 port map (
    Z0 => \$1N6\,
    A0 => A0,
    A1 => \$1N22\);
  \II_$1I31\: AND2 port map (
    Z0 => \$1N8\,
    A0 => A1,
    A1 => S0);
  \II_$1I35\: OR2 port map (
    Z0 => Z0,
    A0 => \$1N6\,
    A1 => \$1N8\);
  \II_$1I38\: INV port map (
    ZN0 => \$1N22\,
    A0 => S0);
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity OB11 is
port(
  XO0 :  out std_logic;
  A0 :  in std_logic);
end OB11;

architecture beh of OB11 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component XOUTPUT
    port(XO0 :  out std_logic;
    A0 :  in std_logic  );
  end component;
begin
  \II_$1I42\: XOUTPUT port map (
    XO0 => XO0,
    A0 => A0);
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity FD11 is
port(
  Q0 :  out std_logic;
  D0 :  in std_logic;
  CLK :  in std_logic);
end FD11;

architecture beh of FD11 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component DFF_FD
    port(Q :  out std_logic;
    D :  in std_logic;
    CP :  in std_logic;
    R :  in std_logic  );
  end component;
begin
  II_BLK2: DFF_FD port map (
    Q => Q0,
    D => D0,
    CP => CLK,
    R => NN_1);
  NN_2 <= '1';
  NN_1 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity XOR2 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic);
end XOR2;

architecture beh of XOR2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  Z0 <= A0 xor A1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity topcounter is
port(
  FIRST : out std_logic_vector(6 downto 0);
  SECOND : out std_logic_vector(6 downto 0);
  THIRD : out std_logic_vector(6 downto 0);
  FOURTH : out std_logic_vector(6 downto 0);
  CLOCK :  in std_logic);
end topcounter;

architecture beh of topcounter is
  signal ONES : std_logic_vector(3 downto 0);
  signal TENS : std_logic_vector(3 downto 0);
  signal HUNDREDS : std_logic_vector(3 downto 0);
  signal THOUSANDS : std_logic_vector(3 downto 0);
  signal \COUNTER1.ONES_1\ : std_logic_vector(3 downto 0);
  signal \COUNTER1.UN1_TENS_2\ : std_logic_vector(3 downto 0);
  signal \COUNTER1.UN1_HUNDREDS_1\ : std_logic_vector(3 downto 0);
  signal \COUNTER1.ONES_5\ : std_logic_vector(3 downto 1);
  signal HUNDREDS_I_0 : std_logic_vector(3 downto 0);
  signal THOUSANDS_I_0 : std_logic_vector(3 downto 0);
  signal TENS_I_0 : std_logic_vector(3 downto 0);
  signal ONES_I_0 : std_logic_vector(3 downto 0);
  signal FIRST_C : std_logic_vector(6 downto 0);
  signal SECOND_C : std_logic_vector(6 downto 0);
  signal THIRD_C : std_logic_vector(6 downto 0);
  signal FOURTH_C : std_logic_vector(6 downto 0);
  signal VCC : std_logic ;
  signal \COUNTER1.TENS7\ : std_logic ;
  signal \COUNTER1.THOUSANDS_C1\ : std_logic ;
  signal N_10 : std_logic ;
  signal N_14 : std_logic ;
  signal N_17 : std_logic ;
  signal N_23 : std_logic ;
  signal N_27 : std_logic ;
  signal N_30 : std_logic ;
  signal N_36 : std_logic ;
  signal N_40 : std_logic ;
  signal N_43 : std_logic ;
  signal N_61 : std_logic ;
  signal N_62 : std_logic ;
  signal N_63 : std_logic ;
  signal \COUNTER1.THOUSANDS7\ : std_logic ;
  signal \BCD4.N_72\ : std_logic ;
  signal \BCD4.N_81\ : std_logic ;
  signal \BCD4.N_82\ : std_logic ;
  signal \BCD4.N_83\ : std_logic ;
  signal \BCD4.N_85\ : std_logic ;
  signal \BCD4.N_86\ : std_logic ;
  signal \BCD4.N_87\ : std_logic ;
  signal \BCD4.N_90\ : std_logic ;
  signal \BCD4.N_91\ : std_logic ;
  signal \BCD3.N_72\ : std_logic ;
  signal \BCD3.N_81\ : std_logic ;
  signal \BCD3.N_82\ : std_logic ;
  signal \BCD3.N_83\ : std_logic ;
  signal \BCD3.N_85\ : std_logic ;
  signal \BCD3.N_86\ : std_logic ;
  signal \BCD3.N_87\ : std_logic ;
  signal \BCD3.N_90\ : std_logic ;
  signal \BCD3.N_91\ : std_logic ;
  signal \BCD2.N_72\ : std_logic ;
  signal \BCD2.N_81\ : std_logic ;
  signal \BCD2.N_82\ : std_logic ;
  signal \BCD2.N_83\ : std_logic ;
  signal \BCD2.N_85\ : std_logic ;
  signal \BCD2.N_86\ : std_logic ;
  signal \BCD2.N_87\ : std_logic ;
  signal \BCD2.N_90\ : std_logic ;
  signal \BCD2.N_91\ : std_logic ;
  signal \BCD1.N_72\ : std_logic ;
  signal \BCD1.N_81\ : std_logic ;
  signal \BCD1.N_82\ : std_logic ;
  signal \BCD1.N_83\ : std_logic ;
  signal \BCD1.N_85\ : std_logic ;
  signal \BCD1.N_86\ : std_logic ;
  signal \BCD1.N_87\ : std_logic ;
  signal \BCD1.N_90\ : std_logic ;
  signal \BCD1.N_91\ : std_logic ;
  signal \COUNTER1.TENS7_2\ : std_logic ;
  signal \BCD1.N_77\ : std_logic ;
  signal \BCD1.N_96\ : std_logic ;
  signal \BCD1.N_84\ : std_logic ;
  signal \BCD1.N_92\ : std_logic ;
  signal \BCD1.N_74\ : std_logic ;
  signal \BCD1.N_78\ : std_logic ;
  signal \BCD1.N_76\ : std_logic ;
  signal \BCD1.N_89\ : std_logic ;
  signal \BCD1.N_95\ : std_logic ;
  signal \COUNTER1.THOUSANDS_C2\ : std_logic ;
  signal \COUNTER1.THOUSANDS_N3\ : std_logic ;
  signal \COUNTER1.THOUSANDS_N1\ : std_logic ;
  signal \COUNTER1.THOUSANDS_N2\ : std_logic ;
  signal \COUNTER1.UN1_TENS_1_2\ : std_logic ;
  signal \COUNTER1.UN1_TENS_1\ : std_logic ;
  signal N_67 : std_logic ;
  signal \BCD2.N_77\ : std_logic ;
  signal \BCD2.N_96\ : std_logic ;
  signal \BCD2.N_84\ : std_logic ;
  signal \BCD2.N_92\ : std_logic ;
  signal \BCD2.N_74\ : std_logic ;
  signal \BCD2.N_78\ : std_logic ;
  signal \BCD2.N_76\ : std_logic ;
  signal \BCD2.N_89\ : std_logic ;
  signal \BCD2.N_95\ : std_logic ;
  signal \BCD4.N_77\ : std_logic ;
  signal \BCD4.N_96\ : std_logic ;
  signal \BCD4.N_84\ : std_logic ;
  signal \BCD4.N_92\ : std_logic ;
  signal \BCD4.N_74\ : std_logic ;
  signal \BCD4.N_78\ : std_logic ;
  signal \BCD4.N_89\ : std_logic ;
  signal \BCD4.N_73\ : std_logic ;
  signal \BCD4.N_95\ : std_logic ;
  signal \BCD3.N_77\ : std_logic ;
  signal \BCD3.N_76\ : std_logic ;
  signal \BCD3.N_89\ : std_logic ;
  signal \BCD3.N_95\ : std_logic ;
  signal \BCD3.N_73\ : std_logic ;
  signal \BCD3.N_92\ : std_logic ;
  signal \BCD3.N_78\ : std_logic ;
  signal \BCD3.N_74\ : std_logic ;
  signal \BCD3.N_84\ : std_logic ;
  signal \BCD3.N_96\ : std_logic ;
  signal \COUNTER1.THOUSANDS_C1_I_0\ : std_logic ;
  signal \COUNTER1.UN1_TENS_1_I_0\ : std_logic ;
  signal \COUNTER1.TENS7_I\ : std_logic ;
  signal \COUNTER1.UN1_TENS_1_2_I_0\ : std_logic ;
  signal \COUNTER1.TENS7_2_I_0\ : std_logic ;
  signal CLOCK_C : std_logic ;
  signal \BCD3.N_92_I\ : std_logic ;
  signal N_76 : std_logic ;
  signal \BCD3.N_86_I\ : std_logic ;
  signal \BCD3.N_89_I\ : std_logic ;
  signal N_77 : std_logic ;
  signal N_80 : std_logic ;
  signal N_81 : std_logic ;
  signal \BCD3.N_81_I\ : std_logic ;
  signal \BCD3.N_84_I\ : std_logic ;
  signal \BCD4.N_92_I\ : std_logic ;
  signal N_85 : std_logic ;
  signal \BCD4.N_81_I\ : std_logic ;
  signal \BCD4.N_84_I\ : std_logic ;
  signal \BCD4.N_86_I\ : std_logic ;
  signal \BCD4.N_89_I\ : std_logic ;
  signal N_87 : std_logic ;
  signal N_91 : std_logic ;
  signal N_67_I : std_logic ;
  signal \COUNTER1.THOUSANDS7_I\ : std_logic ;
  signal \BCD2.N_92_I\ : std_logic ;
  signal N_96 : std_logic ;
  signal \BCD2.N_81_I\ : std_logic ;
  signal \BCD2.N_84_I\ : std_logic ;
  signal \BCD2.N_86_I\ : std_logic ;
  signal \BCD2.N_89_I\ : std_logic ;
  signal N_98 : std_logic ;
  signal N_101 : std_logic ;
  signal N_102 : std_logic ;
  signal \BCD1.N_92_I\ : std_logic ;
  signal N_103 : std_logic ;
  signal \BCD1.N_81_I\ : std_logic ;
  signal \BCD1.N_84_I\ : std_logic ;
  signal \BCD1.N_86_I\ : std_logic ;
  signal \BCD1.N_89_I\ : std_logic ;
  signal N_105 : std_logic ;
  signal N_108 : std_logic ;
  signal N_109 : std_logic ;
  signal \BCD1.N_85_I\ : std_logic ;
  signal \BCD1.N_90_I\ : std_logic ;
  signal \BCD1.N_91_I\ : std_logic ;
  signal N_110 : std_logic ;
  signal \BCD1.N_87_I\ : std_logic ;
  signal N_111 : std_logic ;
  signal \BCD1.N_82_I\ : std_logic ;
  signal \BCD1.N_83_I\ : std_logic ;
  signal \BCD2.N_85_I\ : std_logic ;
  signal \BCD2.N_90_I\ : std_logic ;
  signal \BCD2.N_91_I\ : std_logic ;
  signal N_113 : std_logic ;
  signal \BCD2.N_87_I\ : std_logic ;
  signal N_114 : std_logic ;
  signal \BCD2.N_82_I\ : std_logic ;
  signal \BCD2.N_83_I\ : std_logic ;
  signal \BCD3.N_85_I\ : std_logic ;
  signal \BCD3.N_90_I\ : std_logic ;
  signal \BCD3.N_91_I\ : std_logic ;
  signal N_116 : std_logic ;
  signal \BCD3.N_87_I\ : std_logic ;
  signal N_117 : std_logic ;
  signal \BCD3.N_82_I\ : std_logic ;
  signal \BCD3.N_83_I\ : std_logic ;
  signal \BCD4.N_85_I\ : std_logic ;
  signal \BCD4.N_90_I\ : std_logic ;
  signal \BCD4.N_91_I\ : std_logic ;
  signal N_119 : std_logic ;
  signal \BCD4.N_87_I\ : std_logic ;
  signal N_120 : std_logic ;
  signal \BCD4.N_82_I\ : std_logic ;
  signal \BCD4.N_83_I\ : std_logic ;
  signal \BCD4.N_65_I_0_C\ : std_logic ;
  signal \BCD4.N_67_I_0_C\ : std_logic ;
  signal \BCD3.N_65_I_0_C\ : std_logic ;
  signal \BCD3.N_67_I_0_C\ : std_logic ;
  signal \BCD2.N_65_I_0_C\ : std_logic ;
  signal \BCD2.N_67_I_0_C\ : std_logic ;
  signal \BCD1.N_65_I_0_C\ : std_logic ;
  signal \BCD1.N_67_I_0_C\ : std_logic ;
  signal \BCD3.N_74_I\ : std_logic ;
  signal \BCD3.N_73_I\ : std_logic ;
  signal \BCD4.N_73_I\ : std_logic ;
  signal \BCD4.N_74_I\ : std_logic ;
  signal N_61_I_0 : std_logic ;
  signal \BCD2.N_74_I\ : std_logic ;
  signal \BCD1.N_74_I\ : std_logic ;
  signal \BCD1.N_72_I\ : std_logic ;
  signal \BCD2.N_72_I\ : std_logic ;
  signal \BCD3.N_72_I\ : std_logic ;
  signal \BCD4.N_72_I\ : std_logic ;
  signal N_58_I : std_logic ;
  signal N_56_I : std_logic ;
  signal N_54_I : std_logic ;
  signal N_52_I : std_logic ;
  signal N_141 : std_logic ;
  signal N_142 : std_logic ;
  signal N_143 : std_logic ;
  signal N_144 : std_logic ;
  signal N_145 : std_logic ;
  signal N_146 : std_logic ;
  signal N_147 : std_logic ;
  signal N_148 : std_logic ;
  signal N_149 : std_logic ;
  signal N_150 : std_logic ;
  signal N_151 : std_logic ;
  signal N_152 : std_logic ;
  signal N_153 : std_logic ;
  signal N_154 : std_logic ;
  signal N_155 : std_logic ;
  signal N_156 : std_logic ;
  signal N_157 : std_logic ;
  signal N_158 : std_logic ;
  signal N_159 : std_logic ;
  signal GND : std_logic ;
  component FD11E
    port(Q0 :  out std_logic;
    D0 :  in std_logic;
    CLK :  in std_logic;
    EN :  in std_logic  );
  end component;
  component FD11
    port(Q0 :  out std_logic;
    D0 :  in std_logic;
    CLK :  in std_logic  );
  end component;
  component XOR2
    port(Z0 :  out std_logic;
    A0 :  in std_logic;
    A1 :  in std_logic  );
  end component;
  component AND2
    port(Z0 :  out std_logic;
    A0 :  in std_logic;
    A1 :  in std_logic  );
  end component;
  component OB11
    port(XO0 :  out std_logic;
    A0 :  in std_logic  );
  end component;
  component IB11
    port(Z0 :  out std_logic;
    XI0 :  in std_logic  );
  end component;
  component INV
    port(ZN0 :  out std_logic;
    A0 :  in std_logic  );
  end component;
  component MUX2
    port(Z0 :  out std_logic;
    A0 :  in std_logic;
    A1 :  in std_logic;
    S0 :  in std_logic  );
  end component;
begin
  VCC <= '1';
  \II_COUNTER1.THOUSANDS[3]\: FD11E port map (
    Q0 => THOUSANDS(3),
    D0 => \COUNTER1.THOUSANDS_N3\,
    CLK => CLOCK_C,
    EN => \COUNTER1.THOUSANDS7\);
  \II_COUNTER1.ONES[0]\: FD11 port map (
    Q0 => ONES(0),
    D0 => \COUNTER1.ONES_1\(0),
    CLK => CLOCK_C);
  \II_COUNTER1.ONES[1]\: FD11 port map (
    Q0 => ONES(1),
    D0 => \COUNTER1.ONES_5\(1),
    CLK => CLOCK_C);
  \II_COUNTER1.ONES[2]\: FD11 port map (
    Q0 => ONES(2),
    D0 => \COUNTER1.ONES_1\(2),
    CLK => CLOCK_C);
  \II_COUNTER1.ONES[3]\: FD11 port map (
    Q0 => ONES(3),
    D0 => \COUNTER1.ONES_5\(3),
    CLK => CLOCK_C);
  \II_COUNTER1.TENS[0]\: FD11 port map (
    Q0 => TENS(0),
    D0 => N_52_I,
    CLK => CLOCK_C);
  \II_COUNTER1.TENS[1]\: FD11 port map (
    Q0 => TENS(1),
    D0 => \COUNTER1.UN1_TENS_2\(1),
    CLK => CLOCK_C);
  \II_COUNTER1.TENS[2]\: FD11 port map (
    Q0 => TENS(2),
    D0 => \COUNTER1.UN1_TENS_2\(2),
    CLK => CLOCK_C);
  \II_COUNTER1.TENS[3]\: FD11 port map (
    Q0 => TENS(3),
    D0 => N_54_I,
    CLK => CLOCK_C);
  \II_COUNTER1.HUNDREDS[0]\: FD11 port map (
    Q0 => HUNDREDS(0),
    D0 => N_56_I,
    CLK => CLOCK_C);
  \II_COUNTER1.HUNDREDS[1]\: FD11 port map (
    Q0 => HUNDREDS(1),
    D0 => \COUNTER1.UN1_HUNDREDS_1\(1),
    CLK => CLOCK_C);
  \II_COUNTER1.HUNDREDS[2]\: FD11 port map (
    Q0 => HUNDREDS(2),
    D0 => \COUNTER1.UN1_HUNDREDS_1\(2),
    CLK => CLOCK_C);
  \II_COUNTER1.HUNDREDS[3]\: FD11 port map (
    Q0 => HUNDREDS(3),
    D0 => N_58_I,
    CLK => CLOCK_C);
  \II_COUNTER1.THOUSANDS[0]\: FD11E port map (
    Q0 => THOUSANDS(0),
    D0 => THOUSANDS_I_0(0),
    CLK => CLOCK_C,
    EN => \COUNTER1.THOUSANDS7\);
  \II_COUNTER1.THOUSANDS[1]\: FD11E port map (
    Q0 => THOUSANDS(1),
    D0 => \COUNTER1.THOUSANDS_N1\,
    CLK => CLOCK_C,
    EN => \COUNTER1.THOUSANDS7\);
  \II_COUNTER1.THOUSANDS[2]\: FD11E port map (
    Q0 => THOUSANDS(2),
    D0 => \COUNTER1.THOUSANDS_N2\,
    CLK => CLOCK_C,
    EN => \COUNTER1.THOUSANDS7\);
  II_I_7: XOR2 port map (
    Z0 => \COUNTER1.UN1_TENS_2\(0),
    A0 => TENS(0),
    A1 => N_62);
  II_I_8: AND2 port map (
    Z0 => N_10,
    A0 => TENS(0),
    A1 => N_62);
  II_I_9: XOR2 port map (
    Z0 => \COUNTER1.UN1_TENS_2\(1),
    A0 => TENS(1),
    A1 => N_10);
  II_I_10: AND2 port map (
    Z0 => N_14,
    A0 => TENS(1),
    A1 => N_10);
  II_I_11: XOR2 port map (
    Z0 => \COUNTER1.UN1_TENS_2\(2),
    A0 => TENS(2),
    A1 => N_14);
  II_I_12: AND2 port map (
    Z0 => N_17,
    A0 => TENS(2),
    A1 => N_14);
  II_I_13: XOR2 port map (
    Z0 => \COUNTER1.UN1_TENS_2\(3),
    A0 => TENS(3),
    A1 => N_17);
  II_I_19: XOR2 port map (
    Z0 => \COUNTER1.UN1_HUNDREDS_1\(0),
    A0 => HUNDREDS(0),
    A1 => N_63);
  II_I_20: AND2 port map (
    Z0 => N_23,
    A0 => HUNDREDS(0),
    A1 => N_63);
  II_I_21: XOR2 port map (
    Z0 => \COUNTER1.UN1_HUNDREDS_1\(1),
    A0 => HUNDREDS(1),
    A1 => N_23);
  II_I_22: AND2 port map (
    Z0 => N_27,
    A0 => HUNDREDS(1),
    A1 => N_23);
  II_I_23: XOR2 port map (
    Z0 => \COUNTER1.UN1_HUNDREDS_1\(2),
    A0 => HUNDREDS(2),
    A1 => N_27);
  II_I_24: AND2 port map (
    Z0 => N_30,
    A0 => HUNDREDS(2),
    A1 => N_27);
  II_I_25: XOR2 port map (
    Z0 => \COUNTER1.UN1_HUNDREDS_1\(3),
    A0 => HUNDREDS(3),
    A1 => N_30);
  II_I_31: XOR2 port map (
    Z0 => \COUNTER1.ONES_1\(0),
    A0 => ONES(0),
    A1 => VCC);
  II_I_32: AND2 port map (
    Z0 => N_36,
    A0 => ONES(0),
    A1 => VCC);
  II_I_33: XOR2 port map (
    Z0 => \COUNTER1.ONES_1\(1),
    A0 => ONES(1),
    A1 => N_36);
  II_I_34: AND2 port map (
    Z0 => N_40,
    A0 => ONES(1),
    A1 => N_36);
  II_I_35: XOR2 port map (
    Z0 => \COUNTER1.ONES_1\(2),
    A0 => ONES(2),
    A1 => N_40);
  II_I_36: AND2 port map (
    Z0 => N_43,
    A0 => ONES(2),
    A1 => N_40);
  II_I_37: XOR2 port map (
    Z0 => \COUNTER1.ONES_1\(3),
    A0 => ONES(3),
    A1 => N_43);
  \II_FIRST[0]\: OB11 port map (
    XO0 => FIRST(0),
    A0 => FIRST_C(0));
  \II_FIRST[1]\: OB11 port map (
    XO0 => FIRST(1),
    A0 => \BCD1.N_65_I_0_C\);
  \II_FIRST[2]\: OB11 port map (
    XO0 => FIRST(2),
    A0 => \BCD1.N_67_I_0_C\);
  \II_FIRST[3]\: OB11 port map (
    XO0 => FIRST(3),
    A0 => FIRST_C(3));
  \II_FIRST[4]\: OB11 port map (
    XO0 => FIRST(4),
    A0 => FIRST_C(4));
  \II_FIRST[5]\: OB11 port map (
    XO0 => FIRST(5),
    A0 => FIRST_C(5));
  \II_FIRST[6]\: OB11 port map (
    XO0 => FIRST(6),
    A0 => FIRST_C(6));
  \II_SECOND[0]\: OB11 port map (
    XO0 => SECOND(0),
    A0 => SECOND_C(0));
  \II_SECOND[1]\: OB11 port map (
    XO0 => SECOND(1),
    A0 => \BCD2.N_65_I_0_C\);
  \II_SECOND[2]\: OB11 port map (
    XO0 => SECOND(2),
    A0 => \BCD2.N_67_I_0_C\);
  \II_SECOND[3]\: OB11 port map (
    XO0 => SECOND(3),
    A0 => SECOND_C(3));
  \II_SECOND[4]\: OB11 port map (
    XO0 => SECOND(4),
    A0 => SECOND_C(4));
  \II_SECOND[5]\: OB11 port map (
    XO0 => SECOND(5),
    A0 => SECOND_C(5));
  \II_SECOND[6]\: OB11 port map (
    XO0 => SECOND(6),
    A0 => SECOND_C(6));
  \II_THIRD[0]\: OB11 port map (
    XO0 => THIRD(0),
    A0 => THIRD_C(0));
  \II_THIRD[1]\: OB11 port map (
    XO0 => THIRD(1),
    A0 => \BCD3.N_65_I_0_C\);
  \II_THIRD[2]\: OB11 port map (
    XO0 => THIRD(2),
    A0 => \BCD3.N_67_I_0_C\);
  \II_THIRD[3]\: OB11 port map (
    XO0 => THIRD(3),
    A0 => THIRD_C(3));
  \II_THIRD[4]\: OB11 port map (
    XO0 => THIRD(4),
    A0 => THIRD_C(4));
  \II_THIRD[5]\: OB11 port map (
    XO0 => THIRD(5),
    A0 => THIRD_C(5));
  \II_THIRD[6]\: OB11 port map (
    XO0 => THIRD(6),
    A0 => THIRD_C(6));
  \II_FOURTH[0]\: OB11 port map (
    XO0 => FOURTH(0),
    A0 => FOURTH_C(0));
  \II_FOURTH[1]\: OB11 port map (
    XO0 => FOURTH(1),
    A0 => \BCD4.N_65_I_0_C\);
  \II_FOURTH[2]\: OB11 port map (
    XO0 => FOURTH(2),
    A0 => \BCD4.N_67_I_0_C\);
  \II_FOURTH[3]\: OB11 port map (
    XO0 => FOURTH(3),
    A0 => FOURTH_C(3));
  \II_FOURTH[4]\: OB11 port map (
    XO0 => FOURTH(4),
    A0 => FOURTH_C(4));
  \II_FOURTH[5]\: OB11 port map (
    XO0 => FOURTH(5),
    A0 => FOURTH_C(5));
  \II_FOURTH[6]\: OB11 port map (
    XO0 => FOURTH(6),
    A0 => FOURTH_C(6));
  II_CLOCK: IB11 port map (
    Z0 => CLOCK_C,
    XI0 => CLOCK);
  \II_BCD2.SEGMENTS_15.G_7_0.G_81\: AND2 port map (
    Z0 => N_151,
    A0 => \BCD2.N_90_I\,
    A1 => \BCD2.N_91_I\);
  \II_BCD2.SEGMENTS_15.G_2_I.G_82\: AND2 port map (
    Z0 => N_152,
    A0 => \BCD2.N_82_I\,
    A1 => \BCD2.N_83_I\);
  \II_BCD1.SEGMENTS_15.G_2_I.G_83\: AND2 port map (
    Z0 => N_153,
    A0 => \BCD1.N_82_I\,
    A1 => \BCD1.N_83_I\);
  \II_BCD1.SEGMENTS_15.G_4_0.G_84\: AND2 port map (
    Z0 => N_154,
    A0 => \BCD1.N_86_I\,
    A1 => \BCD1.N_87_I\);
  \II_BCD1.SEGMENTS_15.G_7_0.G_85\: AND2 port map (
    Z0 => N_155,
    A0 => \BCD1.N_90_I\,
    A1 => \BCD1.N_91_I\);
  \II_BCD4.SEGMENTS_15.G_2_I.G_86\: AND2 port map (
    Z0 => N_156,
    A0 => \BCD4.N_82_I\,
    A1 => \BCD4.N_83_I\);
  \II_BCD4.SEGMENTS_15.G_4_0.G_87\: AND2 port map (
    Z0 => N_157,
    A0 => \BCD4.N_86_I\,
    A1 => \BCD4.N_87_I\);
  \II_BCD4.SEGMENTS_15.G_7_0.G_88\: AND2 port map (
    Z0 => N_158,
    A0 => \BCD4.N_90_I\,
    A1 => \BCD4.N_91_I\);
  \II_BCD3.SEGMENTS_15.G_2_I.G_89\: AND2 port map (
    Z0 => N_159,
    A0 => \BCD3.N_82_I\,
    A1 => \BCD3.N_83_I\);
  \II_BCD3.SEGMENTS_15.G_2_I\: AND2 port map (
    Z0 => \BCD3.N_65_I_0_C\,
    A0 => \BCD3.N_81_I\,
    A1 => N_159);
  \II_BCD4.SEGMENTS_15.G_4_0_AND4_1\: AND2 port map (
    Z0 => \BCD4.N_87\,
    A0 => \BCD4.N_72_I\,
    A1 => N_144);
  \II_BCD4.SEGMENTS_15.G_7_0\: AND2 port map (
    Z0 => N_119,
    A0 => \BCD4.N_85_I\,
    A1 => N_158);
  \II_BCD4.SEGMENTS_15.G_4_0\: AND2 port map (
    Z0 => N_120,
    A0 => \BCD4.N_85_I\,
    A1 => N_157);
  \II_BCD4.SEGMENTS_15.G_2_I\: AND2 port map (
    Z0 => \BCD4.N_65_I_0_C\,
    A0 => \BCD4.N_81_I\,
    A1 => N_156);
  \II_BCD1.SEGMENTS_15.G_4_0_AND4_1.G_71\: AND2 port map (
    Z0 => N_141,
    A0 => ONES(2),
    A1 => ONES_I_0(1));
  \II_G_51.G_72\: AND2 port map (
    Z0 => N_142,
    A0 => HUNDREDS(0),
    A1 => HUNDREDS(3));
  \II_COUNTER1.UN1_TENS_1.G_73\: AND2 port map (
    Z0 => N_143,
    A0 => TENS(0),
    A1 => TENS(3));
  \II_BCD4.SEGMENTS_15.G_4_0_AND4_1.G_74\: AND2 port map (
    Z0 => N_144,
    A0 => THOUSANDS(2),
    A1 => THOUSANDS_I_0(1));
  \II_BCD2.SEGMENTS_15.G_4_0_AND4_1.G_75\: AND2 port map (
    Z0 => N_145,
    A0 => TENS(2),
    A1 => TENS_I_0(1));
  \II_COUNTER1.TENS7.G_76\: AND2 port map (
    Z0 => N_146,
    A0 => ONES(0),
    A1 => ONES(3));
  \II_BCD3.SEGMENTS_15.G_4_0_AND4_1.G_77\: AND2 port map (
    Z0 => N_147,
    A0 => HUNDREDS(2),
    A1 => HUNDREDS_I_0(1));
  \II_BCD3.SEGMENTS_15.G_7_0.G_78\: AND2 port map (
    Z0 => N_148,
    A0 => \BCD3.N_90_I\,
    A1 => \BCD3.N_91_I\);
  \II_BCD3.SEGMENTS_15.G_4_0.G_79\: AND2 port map (
    Z0 => N_149,
    A0 => \BCD3.N_86_I\,
    A1 => \BCD3.N_87_I\);
  \II_BCD2.SEGMENTS_15.G_4_0.G_80\: AND2 port map (
    Z0 => N_150,
    A0 => \BCD2.N_86_I\,
    A1 => \BCD2.N_87_I\);
  \II_BCD4.SEGMENTS_15.N_83_I\: INV port map (
    ZN0 => \BCD4.N_83_I\,
    A0 => \BCD4.N_83\);
  \II_COUNTER1.TENS7\: AND2 port map (
    Z0 => \COUNTER1.TENS7\,
    A0 => \COUNTER1.TENS7_2\,
    A1 => N_146);
  \II_COUNTER1.UN1_TENS_1\: AND2 port map (
    Z0 => \COUNTER1.UN1_TENS_1\,
    A0 => \COUNTER1.UN1_TENS_1_2\,
    A1 => N_143);
  II_G_51: AND2 port map (
    Z0 => N_61_I_0,
    A0 => \BCD3.N_73_I\,
    A1 => N_142);
  \II_BCD1.SEGMENTS_15.G_4_0_AND4_1\: AND2 port map (
    Z0 => \BCD1.N_87\,
    A0 => \BCD1.N_72_I\,
    A1 => N_141);
  \II_BCD1.SEGMENTS_15.G_7_0\: AND2 port map (
    Z0 => N_110,
    A0 => \BCD1.N_85_I\,
    A1 => N_155);
  \II_BCD1.SEGMENTS_15.G_4_0\: AND2 port map (
    Z0 => N_111,
    A0 => \BCD1.N_85_I\,
    A1 => N_154);
  \II_BCD1.SEGMENTS_15.G_2_I\: AND2 port map (
    Z0 => \BCD1.N_65_I_0_C\,
    A0 => \BCD1.N_81_I\,
    A1 => N_153);
  \II_BCD2.SEGMENTS_15.G_4_0_AND4_1\: AND2 port map (
    Z0 => \BCD2.N_87\,
    A0 => \BCD2.N_72_I\,
    A1 => N_145);
  \II_BCD2.SEGMENTS_15.G_7_0\: AND2 port map (
    Z0 => N_113,
    A0 => \BCD2.N_85_I\,
    A1 => N_151);
  \II_BCD2.SEGMENTS_15.G_4_0\: AND2 port map (
    Z0 => N_114,
    A0 => \BCD2.N_85_I\,
    A1 => N_150);
  \II_BCD2.SEGMENTS_15.G_2_I\: AND2 port map (
    Z0 => \BCD2.N_65_I_0_C\,
    A0 => \BCD2.N_81_I\,
    A1 => N_152);
  \II_BCD3.SEGMENTS_15.G_4_0_AND4_1\: AND2 port map (
    Z0 => \BCD3.N_87\,
    A0 => \BCD3.N_72_I\,
    A1 => N_147);
  \II_BCD3.SEGMENTS_15.G_7_0\: AND2 port map (
    Z0 => N_116,
    A0 => \BCD3.N_85_I\,
    A1 => N_148);
  \II_BCD3.SEGMENTS_15.G_4_0\: AND2 port map (
    Z0 => N_117,
    A0 => \BCD3.N_85_I\,
    A1 => N_149);
  \II_BCD3.SEGMENTS_15.N_85_I\: INV port map (
    ZN0 => \BCD3.N_85_I\,
    A0 => \BCD3.N_85\);
  \II_BCD3.SEGMENTS_15.N_90_I\: INV port map (
    ZN0 => \BCD3.N_90_I\,
    A0 => \BCD3.N_90\);
  \II_BCD3.SEGMENTS_15.N_91_I\: INV port map (
    ZN0 => \BCD3.N_91_I\,
    A0 => \BCD3.N_91\);
  \II_BCD3.SEGMENTS_15.G_7_0_I\: INV port map (
    ZN0 => THIRD_C(6),
    A0 => N_116);
  \II_BCD3.SEGMENTS_15.N_87_I\: INV port map (
    ZN0 => \BCD3.N_87_I\,
    A0 => \BCD3.N_87\);
  \II_BCD3.SEGMENTS_15.G_4_0_I\: INV port map (
    ZN0 => THIRD_C(3),
    A0 => N_117);
  \II_BCD3.SEGMENTS_15.N_82_I\: INV port map (
    ZN0 => \BCD3.N_82_I\,
    A0 => \BCD3.N_82\);
  \II_BCD3.SEGMENTS_15.N_83_I\: INV port map (
    ZN0 => \BCD3.N_83_I\,
    A0 => \BCD3.N_83\);
  \II_BCD4.SEGMENTS_15.N_85_I\: INV port map (
    ZN0 => \BCD4.N_85_I\,
    A0 => \BCD4.N_85\);
  \II_BCD4.SEGMENTS_15.N_90_I\: INV port map (
    ZN0 => \BCD4.N_90_I\,
    A0 => \BCD4.N_90\);
  \II_BCD4.SEGMENTS_15.N_91_I\: INV port map (
    ZN0 => \BCD4.N_91_I\,
    A0 => \BCD4.N_91\);
  \II_BCD4.SEGMENTS_15.G_7_0_I\: INV port map (
    ZN0 => FOURTH_C(6),
    A0 => N_119);
  \II_BCD4.SEGMENTS_15.N_87_I\: INV port map (
    ZN0 => \BCD4.N_87_I\,
    A0 => \BCD4.N_87\);
  \II_BCD4.SEGMENTS_15.G_4_0_I\: INV port map (
    ZN0 => FOURTH_C(3),
    A0 => N_120);
  \II_BCD4.SEGMENTS_15.N_82_I\: INV port map (
    ZN0 => \BCD4.N_82_I\,
    A0 => \BCD4.N_82\);
  \II_BCD1.SEGMENTS_15.N_90_I\: INV port map (
    ZN0 => \BCD1.N_90_I\,
    A0 => \BCD1.N_90\);
  \II_BCD1.SEGMENTS_15.N_91_I\: INV port map (
    ZN0 => \BCD1.N_91_I\,
    A0 => \BCD1.N_91\);
  \II_BCD1.SEGMENTS_15.G_7_0_I\: INV port map (
    ZN0 => FIRST_C(6),
    A0 => N_110);
  \II_BCD1.SEGMENTS_15.N_87_I\: INV port map (
    ZN0 => \BCD1.N_87_I\,
    A0 => \BCD1.N_87\);
  \II_BCD1.SEGMENTS_15.G_4_0_I\: INV port map (
    ZN0 => FIRST_C(3),
    A0 => N_111);
  \II_BCD1.SEGMENTS_15.N_82_I\: INV port map (
    ZN0 => \BCD1.N_82_I\,
    A0 => \BCD1.N_82\);
  \II_BCD1.SEGMENTS_15.N_83_I\: INV port map (
    ZN0 => \BCD1.N_83_I\,
    A0 => \BCD1.N_83\);
  \II_BCD2.SEGMENTS_15.N_85_I\: INV port map (
    ZN0 => \BCD2.N_85_I\,
    A0 => \BCD2.N_85\);
  \II_BCD2.SEGMENTS_15.N_90_I\: INV port map (
    ZN0 => \BCD2.N_90_I\,
    A0 => \BCD2.N_90\);
  \II_BCD2.SEGMENTS_15.N_91_I\: INV port map (
    ZN0 => \BCD2.N_91_I\,
    A0 => \BCD2.N_91\);
  \II_BCD2.SEGMENTS_15.G_7_0_I\: INV port map (
    ZN0 => SECOND_C(6),
    A0 => N_113);
  \II_BCD2.SEGMENTS_15.N_87_I\: INV port map (
    ZN0 => \BCD2.N_87_I\,
    A0 => \BCD2.N_87\);
  \II_BCD2.SEGMENTS_15.G_4_0_I\: INV port map (
    ZN0 => SECOND_C(3),
    A0 => N_114);
  \II_BCD2.SEGMENTS_15.N_82_I\: INV port map (
    ZN0 => \BCD2.N_82_I\,
    A0 => \BCD2.N_82\);
  \II_BCD2.SEGMENTS_15.N_83_I\: INV port map (
    ZN0 => \BCD2.N_83_I\,
    A0 => \BCD2.N_83\);
  \II_BCD2.G_72_I\: INV port map (
    ZN0 => \BCD2.N_74\,
    A0 => \BCD2.N_74_I\);
  \II_BCD2.G_74_I\: INV port map (
    ZN0 => \BCD2.N_76\,
    A0 => N_101);
  \II_BCD2.G_76_I\: INV port map (
    ZN0 => \BCD2.N_78\,
    A0 => N_102);
  \II_BCD1.N_92_I\: INV port map (
    ZN0 => \BCD1.N_92_I\,
    A0 => \BCD1.N_92\);
  \II_BCD1.SEGMENTS_15.G_1_0_I\: INV port map (
    ZN0 => FIRST_C(0),
    A0 => N_103);
  \II_BCD1.SEGMENTS_15.N_81_I\: INV port map (
    ZN0 => \BCD1.N_81_I\,
    A0 => \BCD1.N_81\);
  \II_BCD1.SEGMENTS_15.N_84_I\: INV port map (
    ZN0 => \BCD1.N_84_I\,
    A0 => \BCD1.N_84\);
  \II_BCD1.SEGMENTS_15.N_86_I\: INV port map (
    ZN0 => \BCD1.N_86_I\,
    A0 => \BCD1.N_86\);
  \II_BCD1.SEGMENTS_15.N_89_I\: INV port map (
    ZN0 => \BCD1.N_89_I\,
    A0 => \BCD1.N_89\);
  \II_BCD1.SEGMENTS_15.G_6_0_I\: INV port map (
    ZN0 => FIRST_C(5),
    A0 => N_105);
  \II_BCD1.G_70_I\: INV port map (
    ZN0 => \BCD1.N_72\,
    A0 => \BCD1.N_72_I\);
  \II_BCD1.G_72_I\: INV port map (
    ZN0 => \BCD1.N_74\,
    A0 => \BCD1.N_74_I\);
  \II_BCD1.G_74_I\: INV port map (
    ZN0 => \BCD1.N_76\,
    A0 => N_108);
  \II_BCD1.G_76_I\: INV port map (
    ZN0 => \BCD1.N_78\,
    A0 => N_109);
  \II_BCD1.SEGMENTS_15.N_85_I\: INV port map (
    ZN0 => \BCD1.N_85_I\,
    A0 => \BCD1.N_85\);
  \II_BCD4.SEGMENTS_15.G_6_0_I\: INV port map (
    ZN0 => FOURTH_C(5),
    A0 => N_87);
  \II_BCD4.G_70_I\: INV port map (
    ZN0 => \BCD4.N_72\,
    A0 => \BCD4.N_72_I\);
  \II_BCD4.G_71_I\: INV port map (
    ZN0 => \BCD4.N_73\,
    A0 => \BCD4.N_73_I\);
  \II_BCD4.G_72_I\: INV port map (
    ZN0 => \BCD4.N_74\,
    A0 => \BCD4.N_74_I\);
  \II_BCD4.G_76_I\: INV port map (
    ZN0 => \BCD4.N_78\,
    A0 => N_91);
  II_N_67_I: INV port map (
    ZN0 => N_67_I,
    A0 => N_67);
  \II_COUNTER1.THOUSANDS7_I\: INV port map (
    ZN0 => \COUNTER1.THOUSANDS7_I\,
    A0 => \COUNTER1.THOUSANDS7\);
  \II_BCD2.N_92_I\: INV port map (
    ZN0 => \BCD2.N_92_I\,
    A0 => \BCD2.N_92\);
  \II_BCD2.SEGMENTS_15.G_1_0_I\: INV port map (
    ZN0 => SECOND_C(0),
    A0 => N_96);
  \II_BCD2.SEGMENTS_15.N_81_I\: INV port map (
    ZN0 => \BCD2.N_81_I\,
    A0 => \BCD2.N_81\);
  \II_BCD2.SEGMENTS_15.N_84_I\: INV port map (
    ZN0 => \BCD2.N_84_I\,
    A0 => \BCD2.N_84\);
  \II_BCD2.SEGMENTS_15.N_86_I\: INV port map (
    ZN0 => \BCD2.N_86_I\,
    A0 => \BCD2.N_86\);
  \II_BCD2.SEGMENTS_15.N_89_I\: INV port map (
    ZN0 => \BCD2.N_89_I\,
    A0 => \BCD2.N_89\);
  \II_BCD2.SEGMENTS_15.G_6_0_I\: INV port map (
    ZN0 => SECOND_C(5),
    A0 => N_98);
  \II_BCD2.G_70_I\: INV port map (
    ZN0 => \BCD2.N_72\,
    A0 => \BCD2.N_72_I\);
  \II_BCD3.SEGMENTS_15.G_6_0_I\: INV port map (
    ZN0 => THIRD_C(5),
    A0 => N_77);
  \II_BCD3.G_70_I\: INV port map (
    ZN0 => \BCD3.N_72\,
    A0 => \BCD3.N_72_I\);
  \II_BCD3.G_71_I\: INV port map (
    ZN0 => \BCD3.N_73\,
    A0 => \BCD3.N_73_I\);
  \II_BCD3.G_74_I\: INV port map (
    ZN0 => \BCD3.N_76\,
    A0 => N_80);
  \II_BCD3.G_76_I\: INV port map (
    ZN0 => \BCD3.N_78\,
    A0 => N_81);
  \II_BCD3.G_72_I\: INV port map (
    ZN0 => \BCD3.N_74\,
    A0 => \BCD3.N_74_I\);
  \II_BCD3.SEGMENTS_15.N_81_I\: INV port map (
    ZN0 => \BCD3.N_81_I\,
    A0 => \BCD3.N_81\);
  \II_BCD3.SEGMENTS_15.N_84_I\: INV port map (
    ZN0 => \BCD3.N_84_I\,
    A0 => \BCD3.N_84\);
  II_G_51_I: INV port map (
    ZN0 => N_61,
    A0 => N_61_I_0);
  \II_BCD4.N_92_I\: INV port map (
    ZN0 => \BCD4.N_92_I\,
    A0 => \BCD4.N_92\);
  \II_BCD4.SEGMENTS_15.G_1_0_I\: INV port map (
    ZN0 => FOURTH_C(0),
    A0 => N_85);
  \II_BCD4.SEGMENTS_15.N_81_I\: INV port map (
    ZN0 => \BCD4.N_81_I\,
    A0 => \BCD4.N_81\);
  \II_BCD4.SEGMENTS_15.N_84_I\: INV port map (
    ZN0 => \BCD4.N_84_I\,
    A0 => \BCD4.N_84\);
  \II_BCD4.SEGMENTS_15.N_86_I\: INV port map (
    ZN0 => \BCD4.N_86_I\,
    A0 => \BCD4.N_86\);
  \II_BCD4.SEGMENTS_15.N_89_I\: INV port map (
    ZN0 => \BCD4.N_89_I\,
    A0 => \BCD4.N_89\);
  \II_BCD3.N_92_I\: INV port map (
    ZN0 => \BCD3.N_92_I\,
    A0 => \BCD3.N_92\);
  \II_BCD3.SEGMENTS_15.G_1_0_I\: INV port map (
    ZN0 => THIRD_C(0),
    A0 => N_76);
  \II_BCD3.SEGMENTS_15.N_86_I\: INV port map (
    ZN0 => \BCD3.N_86_I\,
    A0 => \BCD3.N_86\);
  \II_BCD3.SEGMENTS_15.N_89_I\: INV port map (
    ZN0 => \BCD3.N_89_I\,
    A0 => \BCD3.N_89\);
  \II_COUNTER1.TENS_I[1]\: INV port map (
    ZN0 => TENS_I_0(1),
    A0 => TENS(1));
  \II_COUNTER1.TENS_I[2]\: INV port map (
    ZN0 => TENS_I_0(2),
    A0 => TENS(2));
  \II_COUNTER1.UN1_TENS_1_I\: INV port map (
    ZN0 => \COUNTER1.UN1_TENS_1_I_0\,
    A0 => \COUNTER1.UN1_TENS_1\);
  \II_COUNTER1.TENS7_I\: INV port map (
    ZN0 => \COUNTER1.TENS7_I\,
    A0 => \COUNTER1.TENS7\);
  \II_COUNTER1.TENS_I[3]\: INV port map (
    ZN0 => TENS_I_0(3),
    A0 => TENS(3));
  \II_COUNTER1.TENS_I[0]\: INV port map (
    ZN0 => TENS_I_0(0),
    A0 => TENS(0));
  \II_COUNTER1.UN1_TENS_1_2_I\: INV port map (
    ZN0 => \COUNTER1.UN1_TENS_1_2_I_0\,
    A0 => \COUNTER1.UN1_TENS_1_2\);
  \II_COUNTER1.ONES_I[1]\: INV port map (
    ZN0 => ONES_I_0(1),
    A0 => ONES(1));
  \II_COUNTER1.ONES_I[2]\: INV port map (
    ZN0 => ONES_I_0(2),
    A0 => ONES(2));
  \II_COUNTER1.ONES_I[3]\: INV port map (
    ZN0 => ONES_I_0(3),
    A0 => ONES(3));
  \II_COUNTER1.ONES_I[0]\: INV port map (
    ZN0 => ONES_I_0(0),
    A0 => ONES(0));
  \II_COUNTER1.TENS7_2_I\: INV port map (
    ZN0 => \COUNTER1.TENS7_2_I_0\,
    A0 => \COUNTER1.TENS7_2\);
  \II_BCD3.G_71\: AND2 port map (
    Z0 => \BCD3.N_73_I\,
    A0 => HUNDREDS_I_0(1),
    A1 => HUNDREDS_I_0(2));
  \II_BCD3.G_70\: AND2 port map (
    Z0 => \BCD3.N_72_I\,
    A0 => HUNDREDS_I_0(3),
    A1 => HUNDREDS(0));
  \II_BCD3.SEGMENTS_15.G_6_0\: AND2 port map (
    Z0 => N_77,
    A0 => \BCD3.N_86_I\,
    A1 => \BCD3.N_89_I\);
  \II_BCD3.SEGMENTS_15.G_1_0\: AND2 port map (
    Z0 => N_76,
    A0 => \BCD3.N_92_I\,
    A1 => \BCD3.N_77\);
  \II_BCD3.G_68\: AND2 port map (
    Z0 => \BCD3.N_95\,
    A0 => HUNDREDS(2),
    A1 => HUNDREDS_I_0(3));
  \II_BCD3.G_65\: AND2 port map (
    Z0 => \BCD3.N_92\,
    A0 => HUNDREDS(1),
    A1 => HUNDREDS_I_0(3));
  \II_COUNTER1.HUNDREDS_I[3]\: INV port map (
    ZN0 => HUNDREDS_I_0(3),
    A0 => HUNDREDS(3));
  \II_COUNTER1.HUNDREDS_I[0]\: INV port map (
    ZN0 => HUNDREDS_I_0(0),
    A0 => HUNDREDS(0));
  \II_COUNTER1.HUNDREDS_I[1]\: INV port map (
    ZN0 => HUNDREDS_I_0(1),
    A0 => HUNDREDS(1));
  \II_COUNTER1.HUNDREDS_I[2]\: INV port map (
    ZN0 => HUNDREDS_I_0(2),
    A0 => HUNDREDS(2));
  \II_COUNTER1.THOUSANDS_I[3]\: INV port map (
    ZN0 => THOUSANDS_I_0(3),
    A0 => THOUSANDS(3));
  \II_COUNTER1.THOUSANDS_I[0]\: INV port map (
    ZN0 => THOUSANDS_I_0(0),
    A0 => THOUSANDS(0));
  \II_COUNTER1.THOUSANDS_I[2]\: INV port map (
    ZN0 => THOUSANDS_I_0(2),
    A0 => THOUSANDS(2));
  \II_COUNTER1.THOUSANDS_I[1]\: INV port map (
    ZN0 => THOUSANDS_I_0(1),
    A0 => THOUSANDS(1));
  \II_COUNTER1.THOUSANDS_C1_I\: INV port map (
    ZN0 => \COUNTER1.THOUSANDS_C1_I_0\,
    A0 => \COUNTER1.THOUSANDS_C1\);
  \II_BCD3.SEGMENTS_15.G_3_I\: AND2 port map (
    Z0 => \BCD3.N_67_I_0_C\,
    A0 => \BCD3.N_81_I\,
    A1 => \BCD3.N_84_I\);
  \II_BCD3.G_72\: AND2 port map (
    Z0 => \BCD3.N_74_I\,
    A0 => HUNDREDS(2),
    A1 => HUNDREDS(0));
  \II_BCD3.G_76\: AND2 port map (
    Z0 => N_81,
    A0 => \BCD3.N_73\,
    A1 => \BCD3.N_92_I\);
  \II_BCD3.SEGMENTS_15.G_2_I_AND4_1\: AND2 port map (
    Z0 => \BCD3.N_83\,
    A0 => HUNDREDS(2),
    A1 => \BCD3.N_96\);
  \II_BCD3.SEGMENTS_15.G_3_I_AND4\: AND2 port map (
    Z0 => \BCD3.N_84\,
    A0 => HUNDREDS_I_0(2),
    A1 => \BCD3.N_96\);
  \II_BCD3.SEGMENTS_15.G_5_0_AND4\: AND2 port map (
    Z0 => THIRD_C(4),
    A0 => HUNDREDS_I_0(0),
    A1 => \BCD3.N_78\);
  \II_BCD3.SEGMENTS_15.G_7_0_AND4_0\: AND2 port map (
    Z0 => \BCD3.N_91\,
    A0 => HUNDREDS_I_0(1),
    A1 => \BCD3.N_95\);
  \II_BCD3.SEGMENTS_15.G_7_0_AND4\: AND2 port map (
    Z0 => \BCD3.N_90\,
    A0 => HUNDREDS(3),
    A1 => \BCD3.N_73_I\);
  \II_BCD3.SEGMENTS_15.G_6_0_AND4\: AND2 port map (
    Z0 => \BCD3.N_89\,
    A0 => \BCD3.N_95\,
    A1 => \BCD3.N_76\);
  \II_BCD3.SEGMENTS_15.G_4_0_AND4_0\: AND2 port map (
    Z0 => \BCD3.N_86\,
    A0 => \BCD3.N_73_I\,
    A1 => \BCD3.N_72\);
  \II_BCD3.SEGMENTS_15.G_4_0_AND4\: AND2 port map (
    Z0 => \BCD3.N_85\,
    A0 => \BCD3.N_92\,
    A1 => \BCD3.N_74\);
  \II_BCD3.SEGMENTS_15.G_2_I_AND4_0\: AND2 port map (
    Z0 => \BCD3.N_82\,
    A0 => HUNDREDS_I_0(1),
    A1 => \BCD3.N_74_I\);
  \II_BCD3.SEGMENTS_15.G_2_I_AND4\: AND2 port map (
    Z0 => \BCD3.N_81\,
    A0 => HUNDREDS(3),
    A1 => \BCD3.N_73\);
  \II_BCD3.G_75\: MUX2 port map (
    Z0 => \BCD3.N_77\,
    A0 => HUNDREDS_I_0(2),
    A1 => \BCD3.N_73\,
    S0 => \BCD3.N_72\);
  \II_BCD3.G_74\: AND2 port map (
    Z0 => N_80,
    A0 => HUNDREDS(1),
    A1 => HUNDREDS(0));
  \II_BCD4.SEGMENTS_15.G_2_I_AND4_0\: AND2 port map (
    Z0 => \BCD4.N_82\,
    A0 => THOUSANDS_I_0(1),
    A1 => \BCD4.N_74_I\);
  \II_BCD4.SEGMENTS_15.G_2_I_AND4\: AND2 port map (
    Z0 => \BCD4.N_81\,
    A0 => THOUSANDS(3),
    A1 => \BCD4.N_73\);
  \II_BCD4.G_76\: AND2 port map (
    Z0 => N_91,
    A0 => \BCD4.N_73\,
    A1 => \BCD4.N_92_I\);
  \II_BCD4.G_75\: MUX2 port map (
    Z0 => \BCD4.N_77\,
    A0 => THOUSANDS_I_0(2),
    A1 => \BCD4.N_73\,
    S0 => \BCD4.N_72\);
  \II_BCD4.G_72\: AND2 port map (
    Z0 => \BCD4.N_74_I\,
    A0 => THOUSANDS(0),
    A1 => THOUSANDS(2));
  \II_BCD4.G_71\: AND2 port map (
    Z0 => \BCD4.N_73_I\,
    A0 => THOUSANDS_I_0(1),
    A1 => THOUSANDS_I_0(2));
  \II_BCD4.G_70\: AND2 port map (
    Z0 => \BCD4.N_72_I\,
    A0 => THOUSANDS(0),
    A1 => THOUSANDS_I_0(3));
  \II_BCD4.SEGMENTS_15.G_6_0\: AND2 port map (
    Z0 => N_87,
    A0 => \BCD4.N_86_I\,
    A1 => \BCD4.N_89_I\);
  \II_BCD4.SEGMENTS_15.G_3_I\: AND2 port map (
    Z0 => \BCD4.N_67_I_0_C\,
    A0 => \BCD4.N_81_I\,
    A1 => \BCD4.N_84_I\);
  \II_BCD4.SEGMENTS_15.G_1_0\: AND2 port map (
    Z0 => N_85,
    A0 => \BCD4.N_92_I\,
    A1 => \BCD4.N_77\);
  \II_BCD4.G_69\: AND2 port map (
    Z0 => \BCD4.N_96\,
    A0 => THOUSANDS(1),
    A1 => THOUSANDS_I_0(0));
  \II_BCD4.G_68\: AND2 port map (
    Z0 => \BCD4.N_95\,
    A0 => THOUSANDS(2),
    A1 => THOUSANDS_I_0(3));
  \II_BCD4.G_65\: AND2 port map (
    Z0 => \BCD4.N_92\,
    A0 => THOUSANDS(1),
    A1 => THOUSANDS_I_0(3));
  \II_COUNTER1.THOUSANDS_C1\: AND2 port map (
    Z0 => \COUNTER1.THOUSANDS_C1\,
    A0 => THOUSANDS(1),
    A1 => THOUSANDS(0));
  \II_BCD3.G_69\: AND2 port map (
    Z0 => \BCD3.N_96\,
    A0 => HUNDREDS(1),
    A1 => HUNDREDS_I_0(0));
  \II_COUNTER1.TENS_7_I[0]\: AND2 port map (
    Z0 => N_52_I,
    A0 => N_67_I,
    A1 => \COUNTER1.UN1_TENS_2\(0));
  II_G_49: AND2 port map (
    Z0 => N_67,
    A0 => \COUNTER1.TENS7\,
    A1 => \COUNTER1.UN1_TENS_1\);
  \II_COUNTER1.UN1_TENS_1_2\: AND2 port map (
    Z0 => \COUNTER1.UN1_TENS_1_2\,
    A0 => TENS_I_0(1),
    A1 => TENS_I_0(2));
  \II_COUNTER1.THOUSANDS_N3\: XOR2 port map (
    Z0 => \COUNTER1.THOUSANDS_N3\,
    A0 => \COUNTER1.THOUSANDS_C2\,
    A1 => THOUSANDS(3));
  \II_COUNTER1.THOUSANDS_C2\: AND2 port map (
    Z0 => \COUNTER1.THOUSANDS_C2\,
    A0 => THOUSANDS(2),
    A1 => \COUNTER1.THOUSANDS_C1\);
  \II_COUNTER1.THOUSANDS_N2\: XOR2 port map (
    Z0 => \COUNTER1.THOUSANDS_N2\,
    A0 => \COUNTER1.THOUSANDS_C1\,
    A1 => THOUSANDS(2));
  \II_COUNTER1.THOUSANDS_N1\: XOR2 port map (
    Z0 => \COUNTER1.THOUSANDS_N1\,
    A0 => THOUSANDS(0),
    A1 => THOUSANDS(1));
  \II_BCD4.SEGMENTS_15.G_7_0_AND4_0\: AND2 port map (
    Z0 => \BCD4.N_91\,
    A0 => THOUSANDS_I_0(1),
    A1 => \BCD4.N_95\);
  \II_BCD4.SEGMENTS_15.G_7_0_AND4\: AND2 port map (
    Z0 => \BCD4.N_90\,
    A0 => THOUSANDS(3),
    A1 => \BCD4.N_73_I\);
  \II_BCD4.SEGMENTS_15.G_6_0_AND4\: AND2 port map (
    Z0 => \BCD4.N_89\,
    A0 => \BCD4.N_95\,
    A1 => \COUNTER1.THOUSANDS_C1_I_0\);
  \II_BCD4.SEGMENTS_15.G_5_0_AND4\: AND2 port map (
    Z0 => FOURTH_C(4),
    A0 => THOUSANDS_I_0(0),
    A1 => \BCD4.N_78\);
  \II_BCD4.SEGMENTS_15.G_4_0_AND4_0\: AND2 port map (
    Z0 => \BCD4.N_86\,
    A0 => \BCD4.N_73_I\,
    A1 => \BCD4.N_72\);
  \II_BCD4.SEGMENTS_15.G_4_0_AND4\: AND2 port map (
    Z0 => \BCD4.N_85\,
    A0 => \BCD4.N_92\,
    A1 => \BCD4.N_74\);
  \II_BCD4.SEGMENTS_15.G_3_I_AND4\: AND2 port map (
    Z0 => \BCD4.N_84\,
    A0 => THOUSANDS_I_0(2),
    A1 => \BCD4.N_96\);
  \II_BCD4.SEGMENTS_15.G_2_I_AND4_1\: AND2 port map (
    Z0 => \BCD4.N_83\,
    A0 => THOUSANDS(2),
    A1 => \BCD4.N_96\);
  \II_BCD2.G_70\: AND2 port map (
    Z0 => \BCD2.N_72_I\,
    A0 => TENS_I_0(3),
    A1 => TENS(0));
  \II_BCD2.SEGMENTS_15.G_6_0\: AND2 port map (
    Z0 => N_98,
    A0 => \BCD2.N_86_I\,
    A1 => \BCD2.N_89_I\);
  \II_BCD2.SEGMENTS_15.G_3_I\: AND2 port map (
    Z0 => \BCD2.N_67_I_0_C\,
    A0 => \BCD2.N_81_I\,
    A1 => \BCD2.N_84_I\);
  \II_BCD2.SEGMENTS_15.G_1_0\: AND2 port map (
    Z0 => N_96,
    A0 => \BCD2.N_92_I\,
    A1 => \BCD2.N_77\);
  \II_BCD2.G_69\: AND2 port map (
    Z0 => \BCD2.N_96\,
    A0 => TENS(1),
    A1 => TENS_I_0(0));
  \II_BCD2.G_68\: AND2 port map (
    Z0 => \BCD2.N_95\,
    A0 => TENS(2),
    A1 => TENS_I_0(3));
  \II_BCD2.G_65\: AND2 port map (
    Z0 => \BCD2.N_92\,
    A0 => TENS(1),
    A1 => TENS_I_0(3));
  \II_COUNTER1.HUNDREDS_7_I_AND2[0]\: AND2 port map (
    Z0 => \COUNTER1.THOUSANDS7\,
    A0 => N_61_I_0,
    A1 => N_67);
  \II_COUNTER1.ONES_5_0_AND2[3]\: AND2 port map (
    Z0 => \COUNTER1.ONES_5\(3),
    A0 => \COUNTER1.TENS7_I\,
    A1 => \COUNTER1.ONES_1\(3));
  \II_COUNTER1.ONES_5_0_AND2[1]\: AND2 port map (
    Z0 => \COUNTER1.ONES_5\(1),
    A0 => \COUNTER1.TENS7_I\,
    A1 => \COUNTER1.ONES_1\(1));
  \II_COUNTER1.UN1_HUNDREDS7_1_0_AND2\: AND2 port map (
    Z0 => N_63,
    A0 => N_61,
    A1 => N_67);
  \II_COUNTER1.UN1_TENS7_0_AND2\: AND2 port map (
    Z0 => N_62,
    A0 => \COUNTER1.TENS7\,
    A1 => \COUNTER1.UN1_TENS_1_I_0\);
  \II_COUNTER1.HUNDREDS_7_I[3]\: AND2 port map (
    Z0 => N_58_I,
    A0 => \COUNTER1.THOUSANDS7_I\,
    A1 => \COUNTER1.UN1_HUNDREDS_1\(3));
  \II_COUNTER1.HUNDREDS_7_I[0]\: AND2 port map (
    Z0 => N_56_I,
    A0 => \COUNTER1.THOUSANDS7_I\,
    A1 => \COUNTER1.UN1_HUNDREDS_1\(0));
  \II_COUNTER1.TENS_7_I[3]\: AND2 port map (
    Z0 => N_54_I,
    A0 => N_67_I,
    A1 => \COUNTER1.UN1_TENS_2\(3));
  \II_COUNTER1.TENS7_2\: AND2 port map (
    Z0 => \COUNTER1.TENS7_2\,
    A0 => ONES_I_0(1),
    A1 => ONES_I_0(2));
  \II_BCD2.SEGMENTS_15.G_7_0_AND4_0\: AND2 port map (
    Z0 => \BCD2.N_91\,
    A0 => TENS_I_0(1),
    A1 => \BCD2.N_95\);
  \II_BCD2.SEGMENTS_15.G_7_0_AND4\: AND2 port map (
    Z0 => \BCD2.N_90\,
    A0 => TENS(3),
    A1 => \COUNTER1.UN1_TENS_1_2\);
  \II_BCD2.SEGMENTS_15.G_6_0_AND4\: AND2 port map (
    Z0 => \BCD2.N_89\,
    A0 => \BCD2.N_95\,
    A1 => \BCD2.N_76\);
  \II_BCD2.SEGMENTS_15.G_5_0_AND4\: AND2 port map (
    Z0 => SECOND_C(4),
    A0 => TENS_I_0(0),
    A1 => \BCD2.N_78\);
  \II_BCD2.SEGMENTS_15.G_4_0_AND4_0\: AND2 port map (
    Z0 => \BCD2.N_86\,
    A0 => \COUNTER1.UN1_TENS_1_2\,
    A1 => \BCD2.N_72\);
  \II_BCD2.SEGMENTS_15.G_4_0_AND4\: AND2 port map (
    Z0 => \BCD2.N_85\,
    A0 => \BCD2.N_92\,
    A1 => \BCD2.N_74\);
  \II_BCD2.SEGMENTS_15.G_3_I_AND4\: AND2 port map (
    Z0 => \BCD2.N_84\,
    A0 => TENS_I_0(2),
    A1 => \BCD2.N_96\);
  \II_BCD2.SEGMENTS_15.G_2_I_AND4_1\: AND2 port map (
    Z0 => \BCD2.N_83\,
    A0 => TENS(2),
    A1 => \BCD2.N_96\);
  \II_BCD2.SEGMENTS_15.G_2_I_AND4_0\: AND2 port map (
    Z0 => \BCD2.N_82\,
    A0 => TENS_I_0(1),
    A1 => \BCD2.N_74_I\);
  \II_BCD2.SEGMENTS_15.G_2_I_AND4\: AND2 port map (
    Z0 => \BCD2.N_81\,
    A0 => TENS(3),
    A1 => \COUNTER1.UN1_TENS_1_2_I_0\);
  \II_BCD2.G_76\: AND2 port map (
    Z0 => N_102,
    A0 => \COUNTER1.UN1_TENS_1_2_I_0\,
    A1 => \BCD2.N_92_I\);
  \II_BCD2.G_75\: MUX2 port map (
    Z0 => \BCD2.N_77\,
    A0 => TENS_I_0(2),
    A1 => \COUNTER1.UN1_TENS_1_2_I_0\,
    S0 => \BCD2.N_72\);
  \II_BCD2.G_74\: AND2 port map (
    Z0 => N_101,
    A0 => TENS(1),
    A1 => TENS(0));
  \II_BCD2.G_72\: AND2 port map (
    Z0 => \BCD2.N_74_I\,
    A0 => TENS(2),
    A1 => TENS(0));
  \II_BCD1.SEGMENTS_15.G_3_I_AND4\: AND2 port map (
    Z0 => \BCD1.N_84\,
    A0 => ONES_I_0(2),
    A1 => \BCD1.N_96\);
  \II_BCD1.SEGMENTS_15.G_2_I_AND4_1\: AND2 port map (
    Z0 => \BCD1.N_83\,
    A0 => ONES(2),
    A1 => \BCD1.N_96\);
  \II_BCD1.SEGMENTS_15.G_2_I_AND4_0\: AND2 port map (
    Z0 => \BCD1.N_82\,
    A0 => ONES_I_0(1),
    A1 => \BCD1.N_74_I\);
  \II_BCD1.SEGMENTS_15.G_2_I_AND4\: AND2 port map (
    Z0 => \BCD1.N_81\,
    A0 => ONES(3),
    A1 => \COUNTER1.TENS7_2_I_0\);
  \II_BCD1.G_76\: AND2 port map (
    Z0 => N_109,
    A0 => \COUNTER1.TENS7_2_I_0\,
    A1 => \BCD1.N_92_I\);
  \II_BCD1.G_75\: MUX2 port map (
    Z0 => \BCD1.N_77\,
    A0 => ONES_I_0(2),
    A1 => \COUNTER1.TENS7_2_I_0\,
    S0 => \BCD1.N_72\);
  \II_BCD1.G_74\: AND2 port map (
    Z0 => N_108,
    A0 => ONES(1),
    A1 => ONES(0));
  \II_BCD1.G_72\: AND2 port map (
    Z0 => \BCD1.N_74_I\,
    A0 => ONES(2),
    A1 => ONES(0));
  \II_BCD1.G_70\: AND2 port map (
    Z0 => \BCD1.N_72_I\,
    A0 => ONES_I_0(3),
    A1 => ONES(0));
  \II_BCD1.SEGMENTS_15.G_6_0\: AND2 port map (
    Z0 => N_105,
    A0 => \BCD1.N_86_I\,
    A1 => \BCD1.N_89_I\);
  \II_BCD1.SEGMENTS_15.G_3_I\: AND2 port map (
    Z0 => \BCD1.N_67_I_0_C\,
    A0 => \BCD1.N_81_I\,
    A1 => \BCD1.N_84_I\);
  \II_BCD1.SEGMENTS_15.G_1_0\: AND2 port map (
    Z0 => N_103,
    A0 => \BCD1.N_92_I\,
    A1 => \BCD1.N_77\);
  \II_BCD1.G_69\: AND2 port map (
    Z0 => \BCD1.N_96\,
    A0 => ONES(1),
    A1 => ONES_I_0(0));
  \II_BCD1.G_68\: AND2 port map (
    Z0 => \BCD1.N_95\,
    A0 => ONES(2),
    A1 => ONES_I_0(3));
  \II_BCD1.G_65\: AND2 port map (
    Z0 => \BCD1.N_92\,
    A0 => ONES(1),
    A1 => ONES_I_0(3));
  \II_BCD1.SEGMENTS_15.G_7_0_AND4_0\: AND2 port map (
    Z0 => \BCD1.N_91\,
    A0 => ONES_I_0(1),
    A1 => \BCD1.N_95\);
  \II_BCD1.SEGMENTS_15.G_7_0_AND4\: AND2 port map (
    Z0 => \BCD1.N_90\,
    A0 => ONES(3),
    A1 => \COUNTER1.TENS7_2\);
  \II_BCD1.SEGMENTS_15.G_6_0_AND4\: AND2 port map (
    Z0 => \BCD1.N_89\,
    A0 => \BCD1.N_95\,
    A1 => \BCD1.N_76\);
  \II_BCD1.SEGMENTS_15.G_5_0_AND4\: AND2 port map (
    Z0 => FIRST_C(4),
    A0 => ONES_I_0(0),
    A1 => \BCD1.N_78\);
  \II_BCD1.SEGMENTS_15.G_4_0_AND4_0\: AND2 port map (
    Z0 => \BCD1.N_86\,
    A0 => \COUNTER1.TENS7_2\,
    A1 => \BCD1.N_72\);
  \II_BCD1.SEGMENTS_15.G_4_0_AND4\: AND2 port map (
    Z0 => \BCD1.N_85\,
    A0 => \BCD1.N_92\,
    A1 => \BCD1.N_74\);
  GND <= '0';
end beh;