#-- Synplicity, Inc.
#-- Synplify version 5.3.2
#-- Project file C:\EC333_Fall2000 digital systems\labs\lab8\counter.isp\topcounter.tc_
#-- Written on Tue Oct 31 12:52:59 2000

#device options
set_option -technology pLSI5K
set_option -part ispLSI5256V
set_option -package LB272
set_option -speed_grade -125

#add_file options
add_file -verilog "c:/isptools/synplify/lib/cpld/lattice.v"
add_file -verilog "c:/isptools/ispsys/generic/verilog/synplify/generic.v"
add_file -verilog "bcd7seg.v"
add_file -verilog "counter.v"
add_file -verilog "topcounter.v"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false
set_option -resource_sharing true

#map options
set_option -frequency 0.000
set_option -top_module topcounter

#simulation options
set_option -write_verilog true
set_option -write_vhdl true

#automatic place and route (vendor) options
set_option -write_apr_constraint true

#MTI Cross Probe options
set_option -mti_root ""

#set result format/file last
project -result_file "topcounter.edn"