$ Start of Compile
#Tue Oct 31 12:52:59 2000

Synplify Verilog Compiler, version 5.3.0, built Dec  7 1999
Copyright (C) 1994-1999, Synplicity Inc.  All Rights Reserved

@I::"c:\isptools\synplify\lib\cpld\lattice.v"
@I::"c:\isptools\ispsys\generic\verilog\synplify\generic.v"
@I::"C:\EC333_Fall2000 digital systems\labs\lab8\counter.isp\bcd7seg.v"
@W:"C:\EC333_Fall2000 digital systems\labs\lab8\counter.isp\bcd7seg.v":4:13:4:20|Port declaration for SEGMENTS specifies a range, but later declarations do not
@I::"C:\EC333_Fall2000 digital systems\labs\lab8\counter.isp\counter.v"
@I::"C:\EC333_Fall2000 digital systems\labs\lab8\counter.isp\topcounter.v"
Verilog syntax check successful!
Selecting top level module topcounter
Synthesizing module bcd_counter
@W:"C:\EC333_Fall2000 digital systems\labs\lab8\counter.isp\counter.v":6:0:6:6|Ignoring initial statement
Synthesizing module bcd_to_seven_segment
@W:"C:\EC333_Fall2000 digital systems\labs\lab8\counter.isp\bcd7seg.v":6:0:6:5|always block should contain at least one event control
Synthesizing module topcounter
@END
Process took 0.5 seconds realtime, 0.5 seconds cputime
Synplify CPLD Technology Mapper, version 5.3.0, built Apr 11 2000
Copyright (C) 1994-1999, Synplicity Inc.  All Rights Reserved
Automatic dissolve at startup in view:work.topcounter(verilog) of COUNTER1(bcd_counter)
@N:"c:\ec333_fall2000 digital systems\labs\lab8\counter.isp\counter.v":13:0:13:5|Found counter in view:work.topcounter(verilog) inst COUNTER1.THOUSANDS[3:0]
---------------------------------------
Resource Usage Report

Simple gate primitives:
FD11E           4 uses
FD11            12 uses
XOR2            15 uses
AND2            142 uses
OB11            28 uses
IB11            1 use
INV             101 uses
MUX2            4 uses


Writing encrypted edif
Mapper successful!
Process took 2.52 seconds realtime, 2.52 seconds cputime