// Fil name	: mol60.v
// Purpose	: Verilog source file for clocked module 60 counter
// Autor	: Jianjian Song
// Date		: 27 October 2000
// Description	: The counter will count up when COUNT_UP is "1" and 
//		: count down when COUNT_DOWN is "1". It will be on hold
//		: if COUNT_DOWN==COUNT_UP.
//		: OVERFLOW=1 if COUNT overflows.
//
module mod60(COUNT_UP, COUNT_DOWN, COUNT, OVERFLOW, CLOCK) ;
// a module 60 counter
parameter	MOD = 60;
parameter	NUMBER_OF_BITS = 6;
input		COUNT_UP, COUNT_DOWN, CLOCK;
output	[NUMBER_OF_BITS:1] 	COUNT;
output		OVERFLOW;
reg		COUNT;
reg		OVERFLOW;
initial
	begin
	COUNT = 5'b11110;
	OVERFLOW = 0;
	end
always@(posedge CLOCK)
	begin
		if (COUNT_UP==1 && COUNT_DOWN==0) COUNT = COUNT+1;
		else if (COUNT_UP==0 && COUNT_DOWN==1) COUNT = COUNT-1;
		else COUNT = COUNT;
		if (COUNT == 5'd60) 
		begin
			OVERFLOW = 1;
			COUNT =0;
		end
	end
endmodule