// demo_codec_rectify.v -- Codec full-wave rectifier demo
// Ed Doering
// 07/20/2000
//
//

//-------------------------------------------------------------------------------

// Uncomment the `define line below *only* if targeting the XStend version 1.3 board
// (the XStend board includes Schmitt trigger inverters between the FPGA
// and each of the four codec control inputs)
`define XSTEND 1


module Demo_Codec_Rectify ( 
	// Loop the codec output back to its input, and do sign inversion along the way

	// Inputs: 
	I$Clock	// 12MHz clock
,
	I$Reset	// Active high asynchronous reset
,
	I$SerialDataFromCodec	// Serial data from codec (connect to 'SDOUT' signal)
,

	// Outputs: 
	O$LeftChannelDataValid	// Indicates when left channel data is valid, active high
,
	O$RightChannelDataValid	// Indicates when right channel data is valid, active high
,
	O$MasterClock	// connect to 'MCLK' of codec
,
	O$LeftRightClock	// connect to 'LRCK' of codec
,
	O$SerialClock	// connect to 'SCLK' of codec
,
	O$SerialDataToCodec	// connect to 'SDIN' of codec
	
`ifdef XSTEND
,
	O$MicroReset	// connect to 8051 microcontroller reset pin
,
	O$RAMOutputEnable	// connect to RAM output enable
`endif

); 

// Port mode declarations:
input	I$Clock;
input	I$Reset;
input	I$SerialDataFromCodec;
output	O$LeftChannelDataValid;
output	O$RightChannelDataValid;
output	O$MasterClock;
output	O$LeftRightClock;
output	O$SerialClock;
output	O$SerialDataToCodec;
`ifdef XSTEND
output	O$MicroReset;
output	O$RAMOutputEnable;
`endif

// Registered variable declarations:
reg	O$LeftChannelDataValid;
reg	O$RightChannelDataValid;

reg	[19:0]	r$Left;
reg	[19:0]	r$Right;

// Wire declarations:
wire	[19:0]	w$Left;
wire	[19:0]	w$Right;
wire	w$MasterClock;
wire	w$LeftRightClock;
wire	w$SerialClock;
wire	w$SerialDataToCodec;


`ifdef XSTEND
// Hold the XS40 micro in reset mode, and disable the RAM output
assign O$MicroReset = 1;
assign O$RAMOutputEnable = 1;

// Invert the four codec signals to cancel out the inverters
assign	O$MasterClock = ~w$MasterClock;
assign	O$LeftRightClock = ~w$LeftRightClock;
assign	O$SerialClock = ~w$SerialClock;
assign	O$SerialDataToCodec = ~w$SerialDataToCodec;
`else
assign	O$MasterClock = w$MasterClock;
assign	O$LeftRightClock = w$LeftRightClock;
assign	O$SerialClock = w$SerialClock;
assign	O$SerialDataToCodec = w$SerialDataToCodec;
`endif


// Instantiate the codec interface, and wire for loopback through a
// signal processor
Codec U1 (
	// Inputs: 
	.I$Clock		( I$Clock ),
	.I$Reset		( I$Reset ),
	.I$LeftChannel		( r$Left ),	
	.I$RightChannel		( r$Right ),
	.I$SerialDataFromCodec	( I$SerialDataFromCodec ),

	// Outputs: 
	.O$LeftChannel		( w$Left ),
	.O$RightChannel		( w$Right ),
	.O$LeftChannelDataValid	( O$LeftChannelDataValid ),
	.O$RightChannelDataValid( O$RightChannelDataValid ),
	.O$MasterClock		( w$MasterClock ),
	.O$LeftRightClock 	( w$LeftRightClock ),
	.O$SerialClock		( w$SerialClock ),
	.O$SerialDataToCodec 	( w$SerialDataToCodec )
);

// Signal processing routine is full-wave rectification -- 
// Test sign bit (MSB), and apply ones's complement (sign inversion)
// if the sign bit indicates a negative number. True sign conversion
// would require the two's complement, which is the same as one's
// complement with a '1' added to the result. Using one's complement
// only produces an error in the LSB, and does not incur the space
// penalty of an adder.
always @ (w$Left) r$Left <= (w$Left[19]==1'b1) ? ~w$Left : w$Left;
always @ (w$Right) r$Right <= (w$Right[19]==1'b1) ? ~w$Right : w$Right;



endmodule