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Lab 8 Pipelined Memory, Branches, Jumps

Objectives

This section is not a list of tasks for you to do. It is a list of skills you will have or things you will know after you complete the lab.

Following completion of this lab you should be able to:

• Add instructions to the implementation of a pipelined processor
• Trace code as it executes through a simulated pipelined processor
• Use waveform diagrams to debug a processor implementation
• Use verilog test benches and a testing framework to test a processor implementation

Guidelines

• Because you will be iteratively adding functionality to one processor module, we strongly recommend that you periodically add and commit your progress to git as a backup.

Your Tasks

Follow this sequence of instructions to complete the lab. This lab will all be done in your D-group repository

1 Add lw and sw to your processor

1. Trace on dp diagram
2. Add any new traced wires to verilog datapath
   • And connect to "B" ports of the memory module instead of making a second memory
3. Add control (or connect it)
   • You'll need a mux in WB for memory or ALUOut
4. Run our tests (tb_Pipe.v)

2 Add lui to your datapath

1. Trace on dp diagram (add any new wires)
2. Add any new traced or drawn wires to verilog datapath
   • specifically watch out for what goes back into the register file
3. Add control (or connect it)
   • You'll need to edit your mux in WB for memory or ALUOut to also include the immediate
4. Write tests (add to tb_Pipe.v and create code, assemble it with your assembler, use it)

3 Add Branches

1. trace beq on the datapath
2. Implement
   • hint: need a mux as input to the PC
3. Add control
4. Run beq test we gave you
5. implement bne, blt, and bge (hint: similar modifications to single-cycle)
6. Run other branch tests we gave you

4 Add jal

1. Trace
2. Implement DP + control
   • hint: datapath is a little like lui
   • hint: input to PC is same as branch
   • hint: linking is a bit hard, might need to keep newPC in your pipeline stage register until WB.
3. Test (run tests we gave you)

5 Add jalr

1. Trace
2. Implement DP + control
   • hint: addr calculation is just like lw/sw
   • need to add to the PC input mux (new source)
3. Test (run tests we gave you)

6 Write and run a bigger test

TODO: tell them to write a test with no hazards and all the instructions.

• Hint: if you need to space instructions out, put independent instructions between the two that caused a dependency. You can add zero to itself as a nop instruction:

    xori x2, x3, 4   # F D X M W
    add  x0, x0, x0  #   F D X M W
    add  x0, x0, x0  #     F D X M W
    add  x0, x0, x0  #       F D X M W
    addi x1, x2, x2  #         F D X M W (x2 is put in the reg file while this is getting fetched)

2. On the worksheet, answer the question to explain why the tests in this lab have no dependencies.

Turn It In

Grading Rubric

General Requirements for all Labs:

1. fits the need
2. discuss performance
3. tests for correctness
4. iteration and documentation

Fill out the Lab Worksheet

In the worksheet, explain how you satisfy each of these items. Some guidelines:

• None of these answers should be more than 100 words.
• For item 1, ??
• For item 2, ??
• For item 3, ??
• For item 4, ??

Lab 8 Rubric items	Possible Points
Lab Worksheet	20
Memory insts and tests	15
LUI and tests	10
SB-Types	20
JAL	10
JALR	10
Custom Tests	10
Extra points	5
Total out of	100

For extra points, you could:

• implement aiupc
• Update your assembler to detect hazards and warn when it generates code with hazards
• write more than one test for part 6

1. Submit your completed Lab Worksheet to gradescope.

2. Lab code will be submitted to your D git repository as new files and committed modifications to the repo we provided you. You must include your name and your teammates' names in a comment at the top of all files you submit.