Name: Date:

HW15 solution

  1. (10 points) Draw the pipeline diagram for the following code running on a pipelined RISC-V processor. Identify all of the data dependencies (draw forwards and stalls).

    add x3, x4, x2    IF   ID   EX   ME   WB
                               |    |
                               v    |
sub x5, x3, x1         IF   ID   EX | ME   WB
                                    |
                                    v
lw  x6, 200(x3)             IF   ID   EX   ME   WB
                                               |
                                               v
add x7, x3, x6                   IF   ID   nop  EX   ME   WB

    Which of the above dependencies are data hazards that will be resolved via forwarding? Which dependencies are data hazards that will cause a stall?

    The sub and lw have a dependency on x3 from the first add, so that value must be forwarded. The second add has a dependency on x6 from lw, but since the data isn't available till the MEM stage, a one cycle stall is needed. The data can be forwarded after the stall.

  1. (10 points) Consider the following code to be run on a pipelined RISC-V processor:

    lw   x4, 4(x5)
lw   x3, 0(x5)
add  x7, x7, x3
addi x5, x5, 4
sw   x6, 0(x5)
add  x8, x8, x4
beq  x7, x8, loop

    a. Reorder the instructions to maximize performance. Performance may already by maximized.

    lw   x4, 4(x5)
lw   x3, 0(x5)
add  x8, x8, x4
add  x7, x7, x3
addi x5, x5, 4
sw   x6, 0(x5)
beq  x7, x8, loop

    b. Reorder the instructions to minimize performance. Performance may already be minimized.

    No change or something like:

    lw   x4, 4(x5)
add  x8, x8, x4
lw   x3, 0(x5)
add  x7, x7, x3
addi x5, x5, 4
sw   x6, 0(x5)
beq  x7, x8, loop

  2. (10 points) We wish to add a variant of the lw (load word) instruction, which increments the index register after loading the word from memory. This instruction (l_inc) corresponds to the following two instructions:

    lw   rd, L(rs1)
addi rs1, rs1, 4

    Describe the changes you would need to make to the datapath. You may need to make major changes to the pipeline! Do your changes affect other instructions?

    Insert a new adder to EX to do the +4. Carry result to WB, add an extra write port to RegFile to accomidate. More forwarding hardware will need to be added to support other instructions interacting with the new one.

    or

    Use the ALU for two cycles. That is, the new instruction gets two EX stages in a row. If the next instruction needs the ALU for EX, stall that instruction. If not, proceed without stall. Similarly, the new instruction would need two writebacks. Again, if the next instruction doesn't need WB, just use the register file for two cycles. Otherwise, stall the next instruction. This would also need new forwarding and hazard logic.

    or

    Add a second EX stage to the pipeline, either before or after the current one, forward control signals as appropriate. The forwarding hardware will need to be updated to support forwarding to this new stage, and this will introduce new possible data hazards that will lead to a stall. This would be an extensible solution that would support more complex instructions in the future.