Lab 2: Making an ALU

This lab will guide you through building and testing an ALU in Xilinx. You should perform this lab in PAIRS.

Goals:

Create a new project in Xilinx
Create an ALU in schematic form
Test your ALU for proper operation

Make sure both your names are on all the files you create or edit for this lab.

Part 1: Building a 1-bit Adder

Start Xilinx ISE 14.7. This is probably on your desktop and looks like a green chevron. You used this in the previous lab.
- It may be on your desktop.
If you can't find it on the desktop, try:
- Start → All Programs → Xilinx Design Tools → ISE Design Suite 14.7 → ISE Design Tools → 64-bit Project Navigator
Create a new project:
- Select "File" → "New Project..." to open the "New Project Wizard."
- In the "Create New Project" dialog:
  - enter "alu" for the "Name"
  - choose the "Location" where you want the project
  - add /work to the end of the "Working Directory" field
  - select "Schematic" as the "Top-Level Source Type"
  and click "Next"
- In the "Project Settings" dialog, enter the following properties:
  - Family: Spartan3E
  - Device: XC3S500E
  - Package: FG320
  - Speed: -4
  - Synthesis Tool: XST (VHDL/Verilog)
  - Simulator: ISim (VHDL/Verilog)
  - Prefered Language: Verilog
  and click "Next".
- Click "Finish" in the "Project Summary" dialog.
Note: You can change the project properties by right clicking on the device (i.e. xc3s500e-4fg320) in the "Hierarchy" section of the "Design" tab and selecting "Design Properties..."
Add a new source to the project. There are a number of ways that you can do this, choose one:
- Right click on the device in the "Hierarchy" section of the "Design" tab and select "New Source..."
- Select "Project"→"New Source..."
- Click the "New Source" icon in the toolbar.
Using any of these options, the "New Source Wizard" should appear.
1. In the "Select Source Type" dialog, select "Schematic", enter "add1b" as the "File name:" and click "Next".
2. In the "Summary" dialog, click "Finish".
In add1b.sch implement the following logic:
```
r = (ci & ~a & ~b) | (~ci & a & ~b) | (~ci & ~a & b) | (ci & a & b)
```
and
```
co = (ci & a) | (ci & b) | (a & b)
```
where a and b are inputs to the adder, ci is the carry-in, r is the result, and co is the carry-out.
- You should build the logic using and gates, or gates and inverters, which are all available in the "Symbols" tab.
- To search for a symbol, type the first part of a symbols name in the "Symbol Name Filter".
- To add a symbol to your schematic, select a symbol in the symbol pane (this will switch to "add symbol" mode) and click in the schematic. Clicking again will place another symbol. Pushing "Esc" or right-clicking will cancel "add symbol" mode.
- To connect the symbols click the "Add Wire" icon (a blue pencil drawing a red wire) in the vertical toolbar. Click and drag in the schematic to specify a wire between a single pair of points. Use clicks (no drag) to specify a sequence of connected wire points. Double click will terminate the sequence.
- To add input and output pins click the "Add I/O Marker" icon (a gate going right and a gate going left) in the vertical toolbar.
- To name the input and output pins, click the "Add Net Name" icon (abc over a blue wire) in the toolbar and fill in "Name" in the "Options" pane.
- To check your schematic click "Check Schematic" from the toolbar.
Try to create your own design. However, if you get stuck, you can take a look at this example.
In the "Design" tab "Implemenetation" view, make sure add1b.sch is selected and set as the top level module (a little green square over two gray squares). Right click and set it if necessary. Then, in the lower half of the panel, double click "Synthesize". Correct any errors.
Create a testbench.
1. At the top of the "Design" tab, select the "Simulation" view.
2. Add a new source to the project.
  - For source type select "Verilog Test Fixture" and filename add1b_tb_0.
  - On the "Associate Source" dialog select "add1b" and click "Next".
  - Click "Finish".
3. In the "Hierarchy" section of the "Design" tab, double-click on add1btb0.v and examine the test bench.
4. Edit the verilog code to fully test the adder.
  - Feel free to change the module name to something more reasonable. I used add1b_tb_0.
  - Delete the following section:
```
'ifdef auto_init
 initial begin
 ci = 0;
 b = 0;
 a = 0;
'endif
```
  - Add the following section in its place:
```
initial begin
  ci = 0;
  b = 0;
  a = 0;
  // Wait 100ns for the simulator to finish initializing
  #100;
  a = 1;
  #1;
  if ((r == 1) && (co == 0))
    $display("okay 1");
  else
    $display("fail 1");
end
```
    Notes on the verilog code:
    - You don't have to worry about fully understanding all of the code.
    - "ci = 0" initializes the signal ci to 0.
      Constants are assumed to be decimal integers unless specified otherwise. For example "4'b0101" specifies a 4-bit binary value and "4'h5" specifies the same thing as a 4-bit hexidecimal value.
    - "#100" causes a delay if 100 time units.
    - "$display" will print a message on the simulation console.
  - Add additional verilog code to the initial block to fully test the adder. Consider copying and pasting some code. You should have several good tests for each operation.
Perform a behavioral simulation of your design using Xilinx's ISim tool.
1. At the top of the "Design" tab, select the "Simulation" view.
2. Make sure that the drop-down right under the view selector is set to "Behavioral".
3. In the "Hierarchy" section of the "Design" tab, select the testbench you wish to run (probably add1b_tb_0)
4. In the "Processes" section of the "Design" tab, expand the "ISim Simulator" entry, and double-click the "Simulate Behavioral Model" entry.
5. In the ISim window select View > Zoom > To Full View to show the entire waveform. You should see green signals related to your design. If you see red or blue signals after the 100ns mark, something is wrong in your testbench or design; close ISim and correct the errors.
6. Verify correct results. Press the 'Play hourglass' symbol in the simulator to step forward. Make sure the waveform is correct. Modify your design if necessary.
7. Close ISim.
Create a schematic symbol for add1b.sch.
- At the top of the "Design" tab, select the "Implementation" view. Select the schematic you wish to build.
- In the "Processes" section of the "Design" tab, expand the "Design Utilities" entry, and double-click the "Create Schematics Symbol" entry.

Part 2: Building a 1-bit ALU

Using the 1-bit adder constructed above, design a 1-bit ALU. The ALU should perform the following operations:

Function	op
and	000
or	001
add	010
subtract	110
set less than	111

Be sure to use the specified operation codes.

Your ALU should have the same inputs and outputs as the 1-bit adder with the addition of a 3-bit op input which specifies which operation to perform.

If you need a 2 input mux, you should use part m2_1. If you need a 4 input mux, you should use part m4_1e, but you also need the VCC part to hook up to the mux's E port. The VCC signal can be considered a constant 1; if you need a constant 0, you can use the gnd symbol.

Subtract should be implemented as discussed in class by taking the 1's complement of b and setting ci of the least significant bit to a. Support for set less then should be included, but won't actually be implemented until later.

A sample design is available here. "Subtract" and "set less than" are not implemented. Notice that the mux has an enable that is wired to VCC (a 1) and that individual bits of the op bus can be referenced as op(n). When using buses in your testbench, you refer to bus wires, use brackets like: op[n].

Create a new schematic named alu1b.sch and enter your design.
Create a new testbench named alu1b_tb_0.v to test your design.
Perform a behavioral simulation of your design. Verify correct results. Modify your design if necessary
Create a symbol for alu1b.sch.

Part 3: Building a 4-bit ALU

Using the 1-bit alu constructed above, design a 4-bit ALU. In addition to the basic operations performed by the 1-bit ALU, the 4-bit ALU should have an overflow detector and a zero detector. Be sure finish implementing subtract and set less than.

Your 4-bit ALU should have 2, 4-bit inputs, a and b, a 3-bit input op, a 4-bit output r, and 2 1-bit outputs, zero and ovfl.

Create a new schematic named alu.sch and enter your design.
Create a new testbench named alu_tb_0.v to test your design.
Perform a behavioral simulation of your design. Verify correct results. Modify your design if necessary
Instructor Verification -- Demonstrate your 4-bit ALU to your instructor. (Instructor Verification Sheet)

Part 4: Going Further (optional)

Extend your alu to 16-bits.
Download aluIO_partial.zip, add your alu to the design, and download to an fpga board. A schematic showing where to add your alu is available here.
The aluIo project is designed to work with a 16-bit alu and displays the inputs, the operation and the results on the lcd display. The north button resets the lcd display, the south button clears the display, the west button writes the display, the rotary switch increments or decrements the current digit of the display, pushing the rotary switch changes the current digit, switch 0 selects the direction when the rotary button is pushed, switch 1 selects which row is displayed, led 7 indicates that the lcd driver is ready, led 6 is the zero detector, and led 5 is overflow.

Finishing the lab

Commit your project to SVN.
- Make sure both of your names are in any code files you created.
- Clean up your project (Select "Cleanup Project Files..." from the "Project" menu)
- Remove the work directory (inside your project directory)
- Add and commit your ALU project files to svn
Submit the Instructor Verification Sheet in hard copy.