CS 490: MIPS2001 Instruction Set Architecture
The following instruction set is a subset of the MIPS R2000 Instruction Set Architecture, code named R2001. In this revision, there is no support for floating point, and many pseudo instructions have been removed.
Arithmetic / Logic Instructions
Addition (Support for
Overflow)
add rd, rs, rt
|
0-5 |
6-10 |
11-15 |
16-20 |
21-25 |
26-31 |
|
opcode |
rs |
rt |
rd |
0 |
funct |
6 5 5 5 5 6
Addition (No
Overflow)
addu rd, rs, rt
|
0-5 |
6-10 |
11-15 |
16-20 |
21-25 |
26-31 |
|
opcode |
rs |
rt |
rd |
0 |
funct |
6 5 5 5 5 6
Addition Immediate
(Support for Overflow)
addi rt, rs, imm
|
0-5 |
6-10 |
11-15 |
16-31 |
|
opcode |
rs |
rt |
immed. |
6 5 5 16
Addition Immediate
(No Overflow)
addu rt, rs, imm
|
0-5 |
6-10 |
11-15 |
16-31 |
|
opcode |
rs |
rt |
immed. |
6 5 5 16
And
and rd, rd, rt
|
0-5 |
6-10 |
11-15 |
16-20 |
21-25 |
26-31 |
|
opcode |
rs |
rt |
rd |
Not Used |
funct |
6 5 5 5 5 6
And Immediate
andi rt, rs, imm
|
0-5 |
6-10 |
11-15 |
16-31 |
|
opcode |
rs |
rt |
immed. |
6 5 5 16
Divide (With
Overflow)
div rs, rt
|
0-5 |
6-10 |
11-15 |
16-25 |
26-31 |
|
opcode |
rs |
rt |
Not Used |
funct |
6 5 5 10 6
Divide (Without
Overflow)
divu rs, rt
|
0-5 |
6-10 |
11-15 |
16-25 |
26-31 |
|
opcode |
rs |
rt |
Not Used |
funct |
6 5 5 10 6
Multiply
mult rs, rt
|
0-5 |
6-10 |
11-15 |
16-25 |
26-31 |
|
opcode |
rs |
rt |
Not Used |
funct |
6 5 5 10 6
Unsigned Multiply
multu rs, rt
|
0-5 |
6-10 |
11-15 |
16-25 |
26-31 |
|
opcode |
rs |
rt |
Not Used |
funct |
6 5 5 10 6
Multiply (No
Overflow)
mul rdest, rsrc1, src2
Pseudo Instruction
Multiply (With
Overflow)
mulo, rdest, rsrc1, rsc2
Pseudo Instruction
NOR
nor rd, rs, rt
|
0-5 |
6-10 |
11-15 |
16-20 |
21-25 |
26-31 |
|
opcode |
rs |
rt |
rd |
Not Used |
funct |
6 5 5 5 5 6
OR
or rd, rs, rt
|
0-5 |
6-10 |
11-15 |
16-20 |
21-25 |
26-31 |
|
opcode |
rs |
rt |
rd |
Not Used |
funct |
6 5 5 5 5 6
OR Immediate
ori rs, rt, imm
|
0-5 |
6-10 |
11-15 |
16-31 |
|
opcode |
rs |
rt |
immed. |
6 5 5 16
Shift Left Logical
sll rd, rt, shamt
|
0-5 |
6-10 |
11-15 |
16-20 |
21-25 |
26-31 |
|
opcode |
rs |
rt |
rd |
shamt |
Not used |
6 5 5 5 5 6
Subtract (With
Overflow)
sub rd, rs, rt
|
0-5 |
6-10 |
11-15 |
16-20 |
21-25 |
26-31 |
|
opcode |
rs |
rt |
rd |
Not Used |
funct |
6 5 5 5 5 6
Subtract (Without
Overflow)
subu rd, rs, rt
|
0-5 |
6-10 |
11-15 |
16-20 |
21-25 |
26-31 |
|
opcode |
rs |
rt |
rd |
Not Used |
funct |
6 5 5 5 5 6
Exclusive OR
xor rd, rs, rt
|
0-5 |
6-10 |
11-15 |
16-20 |
21-25 |
26-31 |
|
opcode |
rs |
rt |
rd |
Not Used |
funct |
6 5 5 5 5 6
XOR Immediate
xori rt, rs, imm
|
0-5 |
6-10 |
11-15 |
16-31 |
|
opcode |
rs |
rt |
immed. |
6 5 5 16
Constant Manipulation Instructions
Load Upper Immediate
lui rt, imm
|
0-5 |
6-10 |
11-15 |
16-31 |
|
opcode |
Rs |
rt |
immed. |
6 5 5 16
Load Immediate
li rdest, imm
Pseudo Instruction
Comparison Instructions
Set Less Than
slt rd, rs, rt
|
0-5 |
6-10 |
11-15 |
16-20 |
21-25 |
26-31 |
|
opcode (000000) |
rs |
rt |
rd |
Not Used |
funct |
6 5 5 5 5 6
Set Less Than
Immediate
slti rt, rs, imm
|
0-5 |
6-10 |
11-15 |
16-31 |
|
opcode |
Rs |
rt |
immed. |
6 5 5 16
Branch Instructions
Branch
b label
Pseudo Instruction
Branch on Equal
beq rs, rt, label
|
0-5 |
6-10 |
11-15 |
16-31 |
|
opcode |
rs |
rt |
address |
6 5 5 16
Branch on Not Equal
bne rs, rt, label
|
0-5 |
6-10 |
11-15 |
16-31 |
|
opcode |
rs |
rt |
address |
6 5 5 16
Jump Instructions
Jump
j target
|
0-5 |
6-32 |
|
opcode |
target |
6 26
Jump and Link
jal target
|
0-5 |
6-32 |
|
opcode |
target |
6 26
Jump and Link
Register
jalr rs, rd
|
0-5 |
6-10 |
11-15 |
16-20 |
21-25 |
26-31 |
|
opcode (000000) |
rs |
rt |
rd |
Not Used |
funct |
6 5 5 5 5 6
Jump Register
jr rs
|
0-5 |
6-10 |
11-25 |
26-31 |
|
opcode |
rs |
Not Used |
8 |
6 5 15 6
Load Instructions
Load Address
la rdest, address
Pseudo Instruction
Load Byte
lb rt, address
|
0-5 |
6-10 |
11-15 |
15-31 |
|
opcode |
rs |
rt |
address |
6 5 5 26
Load unsigned Byte
lbu rt, address
|
0-5 |
6-10 |
11-15 |
15-31 |
|
opcode |
rs |
rt |
address |
6 5 5 26
Load Halfword
lh rt, address
|
0-5 |
6-10 |
11-15 |
15-31 |
|
opcode |
rs |
rt |
address |
6 5 5 26
Load unsigned Halfword
lhu rt, address
|
0-5 |
6-10 |
11-15 |
15-31 |
|
opcode |
rs |
rt |
address |
6 5 5 26
Load Word
lw rt, address
|
0-5 |
6-10 |
11-15 |
15-31 |
|
opcode |
rs |
rt |
address |
6 5 5 26
Store Instructions
Store Byte
sb rt, address
|
0-5 |
6-10 |
11-15 |
15-31 |
|
opcode |
rs |
rt |
address |
6 5 5 26
Store Halfword
sh rt, address
|
0-5 |
6-10 |
11-15 |
15-31 |
|
opcode |
rs |
rt |
address |
6 5 5 26
Store Word
sw rt, address
|
0-5 |
6-10 |
11-15 |
15-31 |
|
opcode |
rs |
rt |
address |
6 5 5 26
Data Movement Instructions
Move
move rdest, rsrc
Pseudo Instruction
Move from hi
mfhi rd
|
0-5 |
6-15 |
16-20 |
21-25 |
26-31 |
|
opcode |
0 |
rd |
0 |
0 |
6 10 5 5 6
Move from lo
mflo rd
|
0-5 |
6-15 |
16-20 |
21-25 |
25-31 |
|
opcode |
0 |
rd |
0 |
0 |
6 10 5 5 6
Move to hi
mthi rs
|
0-5 |
6-10 |
11-25 |
26-31 |
|
opcode |
rs |
0 |
0 |
6 5 15 6
Move to lo
mtlo rs
|
0-5 |
6-10 |
11-25 |
26-31 |
|
opcode |
rs |
0 |
0 |
6 5 15 6