Practical 7 Building a Pipelined Processor

Objectives

This section is not a list of tasks for you to do. It is a list of skills you will have or things you will know after you complete the practical.

Following completion of this practical you should be able to:

Construct a verilog implementation of a very basic pipelined processor that supports R and I-type RISC-V instructions.
Trace code as it executes through a simulated pipelined processor
Use waveform diagrams to debug a processor implementation
Use verilog test benches and a testing framework to test a processor implementation

Because you will be iteratively adding functionality to one processor module, we strongly recommend that you periodically add and commit your progress to git as a backup.
This is a reasonable quick-reference for verilog: Compact Summary

Follow this sequence of instructions to complete the practical. This practical will all be done in your practical-pipe repository

First, identify which group you're in. You can find this on moodle or on catme. Ask your instructor for details.
Next, when you follow the link to get your repo you need to enter your team name exactly as your professor provided it.
- Only the first person in your group to set up the repo needs to do this, later people can select the correct team from the list of teams.
Get your repo at this link. Don't click that link without reading the sentences above.

Trace on the provided DP diagram in the worksheet
Design your pipeline stage registers' contents
- build each, call them IF_ID_Reg, etc. so the instances can be IF_ID or similar.
- For each "thing" in the register, make the output named that thing, and an input should have the same name with an _in suffix. For example:
```
input wire [31:0] inst_in,
output reg [31:0] inst,
```
- Be sure to include the clock as an input.
- In the body of the module, create an always block to copy the inputs to their corresponding outputs.
Create Processor.v that has instances of all your pipeline stage registers
Between the registers, instantiate the components you need
- Register File
- PC
- ALU
- No data memory yet (use DP_Memory.v from practical, but only connect the "A" ports.)
Connect the components to your pipeline stage registers
The Memory cycle will just pass data through from EX_MEM to MEM_WB.
Your WB cycle will refer to the register file in your ID cycle.

Open up the tb_Pipe.v test bench in vs code to see how it works. Notice there are lots of shortcuts that assign register values and check them. These are defined in another file, and to get this test to work with your processor you may need to edit the shortcuts.
Open up pipeline_test_tools.vh in vs code and review the comments. Change any references to subresources of UUT so that they correctly reference your wires, registers, and other components. For example, you may need to change UUT.Reg to something else if your register file instance is not called Reg.
- There will be many comments in that file that give you suggestions of what to change. Read the comments.
Open up test_asm/test_pipe_type_nohaz.asm to look at the provided code you will use for the tests. Each line of code here tests something valuable. Review the code and ensure you understand it.
In the worksheet there is a section for a "Testing Plan". You should pick one line of code from the provided .asm file and add it as an entry in the Testing Plan, following the provided template.
Add a new test entry to the Testing Plan. Think about what kinds of errors could happen as you connect the datapath. Create a new test (not one already in the provided asm file) and describe it in the testing plan using the provided format. You do not need to add this to the testbench.
Justify why the provided set of tests is sufficient to verify your processor works for R-types.

Create a new modelsim project. Call it Processor.mpf or some similar name.
- Add all the .v files
- compile them
- simulate/start the tb_Pipe test bench.
Build a waveform to show all your stages.
- add a divider between each stage to make it clear where the stages are separated.
HINT: typing do opcodes.do in the console will add some new "Radix" values to the "radix" menu. This lets you display opcodes and functs as human-readable words.
Save your waveform file. (DO THIS!)
Run the test bench and fix any errors.
Test R-types using tb_Pipe.v
- Remember, you might need to edit the pipeline_test_tools.vh file to make the tests work

Trace I-types on the worksheet's pipeline datapath diagram (not the same one you traced R-types on).
Add any new traced wires to verilog datapath
Add control (or connect it)
- You'll need an ALUSrc mux
Next, prepare some I-type tests.
- Read the tests we've provided (look in the test_asm folder in your repo for the test_pipe_itype_nohaz.asm file).
- Describe one of these tests in the I-Type testing plan on your worksheet.
- Design a new test you would like to add to the test bench, add it to the Testing Plan on the worksheet. (You do not need to add this test to the actual file.)
- Assemble this asm file with your assembler
- then edit the test_I_type_nohaz() task in tb_Pipe.v to load and use it. Look at the R-type task for an example.
- At the bottom of the tb_Pipe.v test bench, there is an initial block that calls a bunch of sub tasks. Uncomment the line that says test_I_type_nohaz(); and the one after it that clears the pipe.
Run tests
- Recompile everything in modelsim.
- restart the simulation, and run the tests. After the R-type tests complete, the I-type tests should run.
On worksheet, explain why the provided set of instructions is sufficient to test I-types, or how you changed it to be better.

Work ahead (go start Practical 8)

General Requirements for all Practicals:

In the worksheet, answer the questions associated with the general requirements.

Submit your completed Practical Worksheet to gradescope.
Practical code will be submitted to your practical-pipe git repository as new files and committed modifications to the repo we provided you. You must include your name and your teammates' names in a comment at the top of all files you submit.