Name: Date:

HW16

We've seen the lw_inc rd, imm(rs1) instruction on previous homework, this I-type instruction loads a word from memory into rd while also incrementing the number in rs1 by 4. We now want to add this instruction to our pipelined processor.

  1. (9 points) Design a way to add this instruction to the pipelined datapath from class (we'll work from the one with branch logic in the Mem stage, see the images on the next page). There are three main approaches to adding instructions to a pipelined processor: A) add new hardware to existing stages, B) add new stages, C) add new control to reuse exisiting stages (i.e. stalls)

    a. (3 points) Explain how approach A could be used to add this instruction to the processor in just a few sentences. (Give the high-level overview here, you do not need to name wires, list bus widths, etc.)

    b. (3 points) Explain how approach B could be used to add this instruction to the processor.

    c. (3 points) Explain how approach C could be used to add this instruction to the processor.

  1. (10 points) Choose one of the three approaches you described above, add the instruction to the following data path using that approach. Indicate your chosen approach above the datapath. If you are adding a new stage clearly indicate which of the existing stages it goes between, draw it neatly below the datapath, and draw the pipeline stage registers before and after it, indicating all I/O ports that are relevant. Note that this datapath has the branch logic in the Mem stage. You do not need to worry about hazards caused by other instructions as you implement this, just worry about the "normal" execution of the instruction.

    Chosen approach:

  1. (10 points) Choose a different one of the three approaches you described above, add the instruction to the following data path using that approach. Indicate your chosen approach above the datapath. See the note above about new stages.

    Chosen approach:

  1. (10 points) Which approach of the two you designed is better for this instruction, why? You should discuss performance implications in your justification. You may also want to consider data forwarding and other hazards that your design could cause in your discussion.