FPGA
System Design with Verilog
A Workshop Prepared for
Rose-Hulman Ventures
E.R.Doering
August 9, 2001
Workshop
Description:
Field-programmable
gate arrays (FPGAs) have emerged as the method of choice for rapid system prototyping
and short time to market. Modern FPGAs with hundreds of thousands of equivalent
gates can implement complete System-on-Chip (SoC) designs that contain embedded
microprocessors, predesigned functional cores, and custom logic. Hardware
description languages (HDLs) enable the designer to create a system to be
implemented by the FPGA. A designer describes a digital system using an HDL,
and automated hardware synthesis tools translate the HDL description into the
FPGA’s internal configuration.
This
hands-on workshop will provide training in the basic techniques necessary to
design FPGA-based digital systems using the Verilog hardware description
language. The workshop is geared towards engineers who wish to incorporate the
benefits of single-chip system design in their product lines, yet who need
assistance with the learning curve. Basic methods for combinational and
sequential circuit description and simulation will be described, followed by
hands-on laboratory projects to reinforce learning. Workshop attendees will be
presented with a complete FPGA prototyping system, including the XESS XS-40
FPGA board and the Xilinx Student Edition design suite.
About
the Presenter:
Dr.
Edward R. Doering is an Associate Professor of Electrical and Computer Engineering
at Rose-Hulman Institute of Technology. He teaches courses in the areas of
digital systems, circuits, and image processing. He has developed courses in
programmable logic systems design at both the undergraduate and graduate
levels, with the graduate course covering advanced HDL methods for design
verification and digital system-on-chip design methodologies. His research and
project work interests include FPGA systems design, embedded systems, and image
processing.
Workshop
Materials: